SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PACKAGE

• US 20120187564A1
• Filed: 01/13/2012
• Published: 07/26/2012
• Est. Priority Date: 01/26/2011
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kuwata, Makoto, TSUGE, Masatoshi
• Granted Patent: US 8,823,177 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A semiconductor device or semiconductor device package for transmitting a plurality of differential signals, the reliability of which hardly deteriorates. The semiconductor device is an area array semiconductor device in which a plurality of lands (external terminals) including a plurality of lands for transmitting a plurality of differential signals are arrayed in a matrix pattern in the back surface of a wiring substrate. Some of the lands are located in the outermost periphery of the matrix pattern. Some others of the lands are located inward of the outermost periphery of the matrix pattern and in rows next to the outermost periphery. The spacing between lands in a second region between the lands located in the rows next to the outermost periphery and the side surface of the wiring substrate is larger than in a first region in the outermost periphery.

Claims

1. A semiconductor device comprising:

a semiconductor chip having a plurality of electrodes including a plurality of first electrode pairs for a plurality of differential pairs for transmitting a differential signal; and

a wiring substrate having a front surface over which the semiconductor chip is mounted, a back surface opposite to the front surface, a side surface intersecting the front surface and the back surface, and a plurality of external terminals electrically connected to the semiconductor chip and arrayed in a matrix pattern in the back surface,

wherein the external terminals includes;

a plurality of first external terminal pairs electrically connected to the first electrode pairs of the semiconductor chip; and

a plurality of second external terminals electrically connected to a plurality of second electrodes different from the first electrode pairs of the semiconductor chip;

wherein the first external terminal pairs includes;

a third external terminal pair located in an outermost periphery of the matrix pattern in the back surface of the wiring substrate; and

a fourth external terminal pair located inward of the outermost periphery of the matrix pattern and in a row next to the outermost periphery in the back surface of the wiring substrate,

wherein the outermost periphery of the matrix pattern includes;

a first region in which the external terminals are arranged at a first spacing; and

a second region in which the external terminals are arranged at a second spacing larger than the first spacing,

wherein the second region lies between the fourth external terminal pair and the side surface of the wiring substrate.

2. The semiconductor device according to claim 1, wherein the second spacing of the second region is larger than a width of one external terminal of the external terminals located in the outermost periphery.

3. The semiconductor device according to claim 2,

wherein the wiring substrate includes:

a plurality of bonding leads electrically connected to the electrodes of the semiconductor chip in the front surface; and

a plurality of wires for connecting the bonding leads and the external terminals electrically,

wherein the fourth external terminal pair is led outward of the bonding leads through the wires of the wiring substrate in a plan view.

4. The semiconductor device according to claim 3, wherein the wires of the wiring substrate include a plurality of wires and a plurality of interlayer conducting paths which are formed by a build-up technique.

5. The semiconductor device according to claim 1,

wherein the back surface of the wiring substrate is quadrangular and a plurality of the third external terminal pairs and a plurality of the fourth external terminal pairs are arranged along sides of the back surface;

and

wherein the second spacing of the second region is larger than an equivalent to two external terminals of the external terminals located in the outermost periphery.

6. The semiconductor device according to claim 1,

wherein the third external terminal pair and the fourth external terminal pair include a fifth external terminal pair for transmitting a differential signal with a first signal intensity and a sixth external terminal pair for transmitting a differential signal with a second signal intensity higher than the first signal intensity,

wherein the second external terminals are located between the fifth external terminal pair and the sixth external terminal pair.

7. The semiconductor device according to claim 6,

wherein the back surface of the wiring substrate is a quadrangle which has a first side, a second side facing the first side, a third side intersecting the first side and the second side and a fourth side facing the third side;

wherein along the first side and the second side, plurality of the sixth external terminal pairs are located and the fifth external terminal pair is not located; and

wherein along the third side and the fourth side, a plurality of the fifth external terminal pairs are located and the sixth external terminal pair is not located.

8. The semiconductor device according to claim 6,

wherein the back surface of the wiring substrate is a quadrangle which has a first side, a second side facing the first side, a third side intersecting the first side and the second side, and a fourth side facing the third side;

wherein along the first side and the fourth side, a plurality of the sixth external terminal pairs are located and the fifth external terminal pair is not located; and

wherein along the second side and the third side, a plurality of the fifth external terminal pairs are located and the sixth external terminal pair is not located.

9. A semiconductor device package comprising:

a semiconductor device;

an electronic component electrically connected with the semiconductor device through a mounting board wire formed in a mounting board; and

the mounting board over which the semiconductor device and the electronic component are mounted,

wherein the semiconductor device includes;

a semiconductor chip having a plurality of electrodes including a plurality of first electrode pairs for a plurality of differential pairs for transmitting a differential signal; and

a wiring substrate having a front surface over which the semiconductor chip is mounted, a back surface opposite to the front surface, a side surface intersecting the front surface and the back surface, and a plurality of external terminals electrically connected to the semiconductor chip and arrayed in a matrix pattern in the back surface,

wherein the external terminals includes;

a plurality of first external terminal pairs electrically connected to the first electrode pairs of the semiconductor chip; and

a plurality of second external terminals electrically connected to a plurality of second electrodes different from the first electrode pairs of the semiconductor chip;

wherein the first external terminal pairs includes;

a third external terminal pair located in an outermost periphery of the matrix pattern in the back surface of the wiring substrate; and

a fourth external terminal pair located inward of the outermost periphery of the matrix pattern and in a row next to the outermost periphery in the back surface of the wiring substrate,

wherein the outermost periphery of the matrix pattern includes;

a first region in which the external terminals are arranged at a first spacing; and

a second region in which the external terminals are arranged at a second spacing larger than the first spacing, and

wherein the second region lies between the fourth external terminal pair and the side surface of the wiring substrate.

10. The semiconductor device package according to claim 9,

wherein the mounting board includes:

a mounting surface over which the semiconductor device is mounted;

a plurality of wiring layers in each of which a plurality of the mounting board wires are formed; and

a plurality of mounting terminals formed in an uppermost wiring layer among the wiring layers and electrically connected to the external terminals of the semiconductor device,

wherein the mounting terminals includes;

a plurality of first mounting terminal pairs electrically connected to the first external terminal pairs of the semiconductor device; and

a plurality of second mounting terminals electrically connected to the second external terminals of the semiconductor device,

wherein the first mounting terminal pairs includes;

a third mounting terminal pair located in the outermost periphery of the matrix pattern in the back surface of the wiring substrate; and

a fourth mounting terminal pair located inward of the outermost periphery of the matrix pattern and in a row next to the outermost periphery in the back surface of the wiring substrate, and

wherein the first mounting terminal pairs are each electrically connected to the electronic component through the mounting board wires formed in a wiring layer among the wiring layers.

11. The semiconductor device package according to claim 10, wherein the first mounting terminal pairs are each electrically connected to the electronic component through the mounting board wires formed in the uppermost wiring layer, among the wiring layers, in which the mounting terminals are formed.

12. The semiconductor device package according to claim 11,

wherein the wiring layers of the mounting board are electrically connected through a through hole penetrating the wiring layers and an interlayer conducting path formed in the through hole and made of conductor;

and

wherein the first mounting terminal pairs are not connected to the interlayer conducting path.

13. The semiconductor device package according to claim 12,

wherein the second spacing of the second region is larger than a width of one external terminal of the external terminals located in the outermost periphery, and

wherein one or more pairs of the mounting board wires electrically connected to the fourth mounting terminal pair are located in a region facing the second region in the uppermost wiring layer of the mounting board.

14. The semiconductor device package according to claim 13,

wherein the back surface of the wiring substrate is quadrangular and a plurality of the third external terminal pairs and a plurality of the fourth external terminal pairs are arranged along sides of the back surface;

wherein the second spacing of the second region is larger than an equivalent to two external terminals of the external terminals located in the outermost periphery; and

wherein a plurality of pairs of the mounting board wires electrically connected to the fourth mounting terminal pair are located in a region facing the second region in the uppermost wiring layer of the mounting board.

15. The semiconductor device package according to claim 9,

wherein the third external terminal pair and the fourth external terminal pair include a fifth external terminal pair for transmitting a differential signal with a first signal intensity and a sixth external terminal pair for transmitting a differential signal with a second signal intensity higher than the first signal intensity;

and

wherein the second external terminals are located between the fifth external terminal pair and the sixth external terminal pair.

16. The semiconductor device package according to claim 15,

wherein the back surface of the wiring substrate is a quadrangle which has a first side, a second side facing the first side, a third side intersecting the first side and the second side, and a fourth side facing the third side;

wherein along the first side and the second side, a plurality of the sixth external terminal pairs are located and the fifth external terminal pair is not located; and

wherein along the third side and the fourth side, plurality of the fifth external terminal pairs are located and the sixth external terminal pair is not located.

17. The semiconductor device package according to claim 16,

wherein the back surface of the wiring substrate is a quadrangle which has a first side, a second side facing the first side, a third side intersecting the first side and the second side, and a fourth side facing the third side;

wherein along the first side and the fourth side, plurality of the sixth external terminal pairs are located and the fifth external terminal pair is not located; and

wherein along the second side and the third side, plurality of the fifth external terminal pairs are located and the sixth external terminal pair is not located.