Signal Distribution Networks and Related Methods

• US 20120187988A1
• Filed: 10/09/2010
• Published: 07/26/2012
• Est. Priority Date: 10/15/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Rambus Inc.
• Inventors: Aryanfar, Farshid, Lee, Hae-Chang, Chang, Kun-Yung, Wu, Ting, Werner, Carl, Koochakzadeh, Masoud
• Granted Patent: US 8,610,474 B2
• Time in Patent Office: Days
• US Class Current: 327/156
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence

Abstract

A signal distribution network has segments that each have a buffer circuit, a transmission line coupled to the buffer circuit, an inductor coupled to the buffer circuit through the transmission line, and a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the transmission line. A capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the transmission line. A signal distribution network can include a phase detector, a loop filter circuit, and a resonant delay circuit. The phase detector compares a phase of a first periodic signal to a phase of a second periodic signal. The resonant delay circuit has a variable impedance circuit having an impedance that varies based on changes in an output signal of the loop filter circuit.

Claims

1. A circuit comprising segments coupled together to form a signal distribution network, wherein each of the segments comprises:

a buffer circuit;

a first transmission line coupled to the buffer circuit;

an inductor coupled to the buffer circuit through the first transmission line; and

a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the first transmission line, wherein a capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the first transmission line.

2. The circuit of claim 1 wherein the variable capacitance circuit in each of the segments is coupled to a buffer circuit in an adjacent segment through a second transmission line.

3. The circuit of claim 1 wherein the signal distribution network is a differential signal distribution network that comprises a second transmission line coupled to the buffer circuit, the inductor, and the variable capacitance circuit.

4. The circuit of claim 1 wherein the signal distribution network is a single-ended signal distribution network.

5. The circuit of claim 1 wherein the capacitance of the variable capacitance circuit is set to a capacitance that causes an output signal of the buffer circuit to have a zero phase offset relative to an input signal of the buffer circuit.

6. The circuit of claim 1 wherein a gain of the buffer circuit is adjustable.

7. The circuit of claim 6 wherein each of the segments further comprises:

an amplitude detector circuit that adjusts the gain of the buffer circuit based on changes in an output signal of the buffer circuit.

8. The circuit of claim 6 wherein each of the segments further comprises:

an amplitude comparator circuit that adjusts the gain of the buffer circuit based on changes in a difference between an output signal of the buffer circuit and an output signal of a previous segment of the signal distribution network.

9. The circuit of claim 1 wherein at least one of the segments of the signal distribution network comprises a delay-locked loop circuit, and wherein the delay-locked loop circuit comprises the buffer circuit, the first transmission line, the inductor, the variable capacitance circuit, a phase detector coupled to the buffer circuit, and a loop filter coupled to the phase detector and the variable capacitance circuit.

10. The circuit of claim 1 wherein the circuit comprises at least three of the segments coupled together in the signal distribution network.

11. The circuit of claim 1 wherein the inductor is coupled in parallel with the variable capacitance circuit.

12. The circuit of claim 11 wherein a resonant frequency of the inductor, the variable capacitance circuit, and the first transmission line is set to a frequency that is greater than a frequency of a clock signal transmitted through the first transmission line.

13. The circuit of claim 1 wherein the signal distribution network comprises a clock distribution network.

14. The circuit of claim 1 wherein the circuit is embedded in an integrated circuit die.

15. A circuit comprising a signal distribution network, wherein the signal distribution network comprises:

a phase detector that compares a phase of a first periodic signal to a phase of a second periodic signal;

a loop filter circuit coupled to the phase detector; and

a first resonant delay circuit coupled to the loop filter circuit and coupled to the phase detector, wherein the first resonant delay circuit comprises a variable impedance circuit having an impedance that varies based on changes in an output signal of the loop filter circuit.

16. The circuit of claim 15 wherein the variable impedance circuit comprises a circuit having a variable capacitance.

17. The circuit of claim 16 wherein the first resonant delay circuit further comprises an inductor coupled to the circuit having the variable capacitance.

18. The circuit of claim 15 wherein the first resonant delay circuit comprises an inductor.

19. The circuit of claim 15 wherein the first resonant delay circuit comprises a buffer circuit, an inductor, and a variable capacitance circuit.

20. The circuit of claim 15 wherein the phase detector adjusts a delay of the first resonant delay circuit to reduce skew between phases of the first and the second periodic signals.

21. The circuit of claim 15 wherein the loop filter circuit is an accumulator, and wherein the phase detector is a zero phase detector.

22. The circuit of claim 15 wherein the signal distribution network is embedded in an integrated circuit.

23. The circuit of claim 15 wherein the first resonant delay circuit comprises a first buffer circuit, and wherein the signal distribution network further comprises:

a second resonant delay circuit coupled to the loop filter circuit, wherein the second resonant delay circuit comprises a second buffer circuit coupled to the first buffer circuit.

24. The circuit of claim 23 wherein the signal distribution network further comprises:

a third resonant delay circuit coupled to the loop filter circuit, wherein the third resonant delay circuit comprises a third buffer circuit coupled to the second buffer circuit.

25. The circuit of claim 24 wherein the signal distribution network further comprises:

fourth, fifth, and sixth resonant delay circuits coupled in series, coupled to the third resonant delay circuit, and coupled to the loop filter circuit.

26. The circuit of claim 23 wherein the signal distribution network further comprises:

an Nth resonant delay circuit coupled to the loop filter circuit, wherein the Nth resonant delay circuit comprises an Nth buffer circuit that is coupled to the phase detector.

27. The circuit of claim 15 wherein the signal distribution network comprises a delay-locked loop circuit.

28. The circuit of claim 15 wherein a resonant frequency of the first resonant delay circuit is set to a frequency that is greater than frequencies of the first and the second periodic signals.

29. The circuit of claim 15 wherein the signal distribution network comprises a first single-ended transmission line coupled to the phase detector, and a second single-ended transmission line coupled to the first resonant delay circuit.

30. The circuit of claim 15 wherein the signal distribution network comprises differential transmission lines coupled to the phase detector.

31. A method for transmitting a periodic signal through a signal distribution network having segments that are coupled together, the method comprising:

buffering the periodic signal in each of the segments to generate a buffered periodic signal;

transmitting the buffered periodic signal through a first transmission line in each of the segments; and

setting a capacitance of a variable capacitance circuit in each of the segments to select a phase and an amplitude of the buffered periodic signal, wherein the variable capacitance circuit is coupled to an inductor in each of the segments.

32. The method of claim 31 further comprising:

transmitting the buffered periodic signal through a second transmission line in each of the segments.

33. The method of claim 31 wherein a resonant frequency of the variable capacitance circuit, the inductor, and the first transmission line in each of the segments is greater than the frequency of the buffered periodic signal.

34. The method of claim 31 wherein the signal distribution network comprises at least three of the segments.

35. The method of claim 31 wherein the inductor in each of the segments is coupled in parallel with the variable capacitance circuit.

36. The method of claim 31 wherein the signal distribution network is differential, wherein buffering the periodic signal in each of the segments to generate a buffered periodic signal further comprises buffering the periodic signal in each of the segments to generate a differential buffered periodic signal, and wherein transmitting the buffered periodic signal through a first transmission line in each of the segments further comprises transmitting the differential buffered periodic signal through first and second transmission lines in each of the segments.

37. The method of claim 31 wherein the signal distribution network is single-ended.

38. The method of claim 31 wherein the capacitance of the variable capacitance circuit is set to a capacitance that causes the buffered periodic signal to have a zero phase offset relative to the periodic signal.

39. A method for controlling a phase of a periodic signal transmitted through a signal distribution network, wherein the method comprises:

comparing a phase of a first periodic signal with a phase of a second periodic signal to generate a first phase comparison signal;

filtering the first phase comparison signal to generate a first filtered signal; and

setting a first variable impedance in a first resonant delay circuit based on the first filtered signal to determine the phase of the second periodic signal.

40. The method of claim 39 wherein setting a first variable impedance in a first resonant delay circuit based on the first filtered signal to determine the phase of the second periodic signal further comprises setting a capacitance of a variable capacitance circuit in the first resonant delay circuit, and wherein the variable capacitance circuit is coupled to an inductor.

41. The method of claim 39 further comprising:

comparing the phase of the second periodic signal with a phase of a third periodic signal to generate a second phase comparison signal;

filtering the second phase comparison signal to generate a second filtered signal; and

setting a second variable impedance in a second resonant delay circuit based on the second filtered signal to determine the phase of the third periodic signal.

42. The method of claim 41 wherein setting a second variable impedance in a second resonant delay circuit based on the second filtered signal to determine the phase of the third periodic signal further comprises setting a capacitance of a variable capacitance circuit in the second resonant delay circuit, and wherein the variable capacitance circuit is coupled to an inductor.

43. The method of claim 39 wherein a resonant frequency of the first variable impedance combined with a transmission line is greater than frequencies of the first and the second periodic signals.