MEMORY DEVICE AND SEMICONDUCTOR DEVICE

• US 20120188814A1
• Filed: 01/13/2012
• Published: 07/26/2012
• Est. Priority Date: 01/26/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, KOYAMA, Jun
• Granted Patent: US 9,601,178 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

To provide a memory device which operates at high speed or a memory device in which the frequency of refresh operations is reduced. In a cell array, a potential is supplied from a driver circuit to a wiring connected to a memory cell. The cell array is provided over the driver circuit. Each of memory cells included in the cell array includes a switching element, and a capacitor in which supply, holding, and discharge of electric charge are controlled by the switching element. Further, a channel formation region of the transistor used as the switching element includes a semiconductor whose band gap is wider than that of silicon and whose intrinsic carrier density is lower than that of silicon.

Claims

1. A memory device comprising:

a driver circuit; and

a cell array over the driver circuit,

wherein the cell array comprises a plurality of memory cells and a plurality of wirings,

wherein at least one of the plurality of wirings is electrically connected to the plurality of memory cells,

wherein the driver circuit is electrically connected to each of the plurality of wirings at a portion inside the cell array,

wherein the plurality of memory cells each comprise a transistor and a capacitor electrically connected to the transistor, and

wherein the transistor comprises an oxide semiconductor.

2. The memory device according to claim 1, wherein the transistor comprises crystalline silicon or germanium.

3. The memory device according to claim 1, wherein the oxide semiconductor comprises In, Ga, and Zn.

4. The memory device according to claim 1, wherein a hydrogen concentration of the oxide semiconductor is 1×

10¹⁹/cm³ or less.

5. A semiconductor device comprising the memory device according to claim 1.

6. A memory device comprising:

a driver circuit; and

a cell array over the driver circuit,

wherein the cell array comprises a plurality of memory cells arranged in x columns and y rows (x and y are natural numbers of 2 or more) and y word lines,

wherein each of the y word lines is electrically connected to x memory cells in each row,

wherein the driver circuit is electrically connected to each of they word lines at a portion inside the cell array,

wherein the plurality of memory cells each comprise a transistor and a capacitor electrically connected to the transistor, and

wherein the transistor comprises an oxide semiconductor.

7. The memory device according to claim 6, wherein at least one of the y word lines is electrically connected to a gate electrode of the transistor in each of x memory cells.

8. The memory device according to claim 6, wherein the transistor comprises crystalline silicon or germanium.

9. The memory device according to claim 6, wherein the oxide semiconductor comprises In, Ga, and Zn.

10. The memory device according to claim 6, wherein a hydrogen concentration of the oxide semiconductor is 1×

10¹⁹/cm³ or less.

11. A semiconductor device comprising the memory device according to claim 6.

12. A memory device comprising:

a driver circuit; and

a cell array over the driver circuit,

wherein the cell array comprises a plurality of memory cells arranged in x columns and y rows (x and y are natural numbers of 2 or more) and x data lines,

wherein each of the x data lines is electrically connected to y memory cells in each column,

wherein the driver circuit is electrically connected to each of the x data lines at a portion inside the cell array,

wherein the plurality of memory cells each comprise a transistor and a capacitor electrically connected to the transistor, and

wherein the transistor comprises an oxide semiconductor.

13. The memory device according to claim 12,

wherein at least one of the x data lines is electrically connected to a first terminal of the transistor in each of y memory cells, and

wherein a second terminal of the transistor is electrically connected to any one of a pair of electrodes of the capacitor in each of y memory cells.

14. The memory device according to claim 12, wherein the transistor comprises crystalline silicon or germanium.

15. The memory device according to claim 12, wherein the oxide semiconductor comprises In, Ga, and Zn.

16. The memory device according to claim 12, wherein a hydrogen concentration of the oxide semiconductor is 1×

10¹⁹/cm³ or less.

17. A semiconductor device comprising the memory device according to claim 12.

18. A memory device comprising:

a driver circuit; and

a cell array over the driver circuit,

wherein the cell array comprises a plurality of memory cells arranged in x columns and y rows (x and y are natural numbers of 2 or more), y word lines, and x data lines,

wherein each of the y word lines is electrically connected to x memory cells in each row,

wherein each of the x data lines is electrically connected to y memory cells in each column,

wherein the driver circuit is electrically connected to each of they word lines at a first portion inside the cell array,

wherein the driver circuit is electrically connected to each of the x data lines at a second portion inside the cell array,

wherein the plurality of memory cells each comprise a transistor and a capacitor electrically connected to the transistor, and

wherein the transistor comprises an oxide semiconductor.

19. The memory device according to claim 18,

wherein at least one of the y word lines is electrically connected to a gate electrode of the transistor in each of x memory cells,

wherein at least one of the x data lines is electrically connected to a first terminal of the transistor in each of y memory cells, and

wherein a second terminal of the transistor is electrically connected to any one of a pair of electrodes of the capacitor in each of y memory cells.

20. The memory device according to claim 18, wherein the transistor comprises crystalline silicon or germanium.

21. The memory device according to claim 18, wherein the oxide semiconductor comprises In, Ga, and Zn.

22. The memory device according to claim 18, wherein a hydrogen concentration of the oxide semiconductor is 1×

10¹⁹/cm³ or less.

23. A semiconductor device comprising the memory device according to claim 18.