RECESSED GATE CHANNEL WITH LOW Vt CORNER
First Claim
1. A method of forming a recessed gate FET comprising the steps of:
- providing a semiconductor substrate having an upper doped portion and a lower doped portion beneath a substrate surface;
forming a trench in said substrate to define a gate electrode and a channel region surrounding said gate electrode, a bottom corner of said trench extending into said lower doped portion of said substrate;
lining sidewalls and bottom portions of said trench with dielectric material layer;
filling said trench with a material to form a gate conductor;
recessing said gate conductor below a substrate surface to define an opening at an upper portion of said trench;
optionally forming doped pocket regions at either side of and abutting said gate electrode, each doped pocket region extending into said channel region;
providing a dielectric cap in said formed opening; and
forming source and drain diffusion regions at either side of said gate electrode at said substrate surface that contact respective formed doped pocket regions, wherein a bottom portion of said trench is formed in said lower doped portion of said substrate, said recessed gate FET thereby exhibiting improved suppression of short channel effects.
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Accused Products
Abstract
A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate electrode defining a surrounding channel region and having a gate dielectric material layer lining and including a conductive material having a top surface recessed to reduce overlap capacitance with respect to the source and drain diffusion regions formed at an upper substrate surface at either side of the gate electrode. There is optionally formed halo implants at either side of and abutting the gate electrode, each halo implants extending below the source and drain diffusions into the channel region. Additionally, highly doped source and drain extension regions are formed that provide a low resistance path from the source and drain diffusion regions to the channel region.
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Citations
20 Claims
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1. A method of forming a recessed gate FET comprising the steps of:
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providing a semiconductor substrate having an upper doped portion and a lower doped portion beneath a substrate surface; forming a trench in said substrate to define a gate electrode and a channel region surrounding said gate electrode, a bottom corner of said trench extending into said lower doped portion of said substrate; lining sidewalls and bottom portions of said trench with dielectric material layer; filling said trench with a material to form a gate conductor; recessing said gate conductor below a substrate surface to define an opening at an upper portion of said trench; optionally forming doped pocket regions at either side of and abutting said gate electrode, each doped pocket region extending into said channel region; providing a dielectric cap in said formed opening; and forming source and drain diffusion regions at either side of said gate electrode at said substrate surface that contact respective formed doped pocket regions, wherein a bottom portion of said trench is formed in said lower doped portion of said substrate, said recessed gate FET thereby exhibiting improved suppression of short channel effects. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of forming a recessed gate FET comprising the steps of:
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providing a semiconductor substrate having an upper doped portion and a lower doped portion beneath a substrate surface; forming a trench in said substrate to define a gate electrode and a channel region surrounding said gate electrode, a bottom corner of said trench extending into said lower doped portion of said substrate; lining sidewalls and bottom portions of said trench with dielectric material layer; filling said trench with a material to form a gate conductor; recessing said gate conductor below a substrate surface to define an opening at an upper portion of said trench; forming doped pocket regions at either side of and abutting said gate electrode, each doped pocket region extending into said channel region; forming extension regions of highly doped material adjacent an upper portion of said gate electrode within said formed doped pocket regions at either side of said gate electrode; providing a dielectric cap in said formed opening; and forming source and drain diffusion regions at either side of said gate electrode at said substrate surface that contact respective extension regions, said extension regions providing a low resistance path from said source and drain diffusion regions to said channel region, wherein a bottom portion of said trench is formed in said lower doped portion of said substrate, said recessed gate FET thereby exhibiting improved suppression of short channel effects. - View Dependent Claims (12, 13, 14, 15)
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16. A method of forming a recessed gate FET comprising the steps of:
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providing a semiconductor substrate having an upper doped portion and a lower doped portion beneath a substrate surface; providing a thin dielectric layer atop an upper surface of said substrate; forming a trench in said substrate to define a gate electrode and a channel region surrounding said gate electrode, a bottom corner of said trench extending into said lower doped portion of said substrate; filling said trench with sacrificial dielectric material; recessing a portion of said sacrificial dielectric material to a depth below a substrate surface to form an opening in an upper trench portion of said gate electrode; forming extension regions of highly doped material adjacent said upper trench portion of said gate electrode; removing said sacrificial dielectric material from said trench; thermally growing a gate dielectric material layer that lines said sidewall and bottom of said trench; filling said dielectric material lined trench with a conductor material to form a gate conductor; recessing said gate conductor below a substrate surface to define an opening at an upper portion of said trench; providing a dielectric cap in said formed opening; and forming source and drain diffusion regions at either side of said gate electrode at said substrate surface that contact respective extension regions, said extension regions providing a low resistance path from respective source and drain diffusions to said channel region, wherein a bottom portion of said trench is formed in said lower doped portion of said substrate, said recessed gate FET thereby exhibiting improved suppression of short channel effects. - View Dependent Claims (17, 18, 19, 20)
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Specification