DIAGNOSING IN-LINE CRITICAL DIMENSION CONTROL ADJUSTMENTS USING OPTICAL PROXIMITY CORRECTION VERIFICATION

• US 20120191234A1
• Filed: 01/26/2011
• Published: 07/26/2012
• Est. Priority Date: 01/26/2011
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Bruce, James A., Settlemyer, Kenneth T. Jr.
• Granted Patent: US 8,577,489 B2
• Time in Patent Office: Days
• US Class Current: 700/103
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions

Abstract

Solutions for diagnosing in-line critical dimension control adjustments in a lithographic process are disclosed. In one embodiment, a method includes: locating a control structure in a data set representing one of a chip or a kerf; simulating component dimensions within a region proximate to the control structure; determining a difference between the simulated component dimensions within the region and target component dimensions within the region; determining whether the difference exceeds a predetermined tolerance threshold; adjusting a simulation condition in response to determining the difference exceeds the predetermined tolerance threshold; and repeating the simulating of the component dimensions within the region, the determining of the difference, and the determining of whether the difference exceeds the predetermined tolerance threshold in response to the adjusting of the simulation condition.

Claims

1. A computer-implemented method of diagnosing in-line critical dimension control adjustments in a lithographic process, the method comprising:

locating a control structure in a data set representing one of a chip or a kerf;

simulating component dimensions within a region proximate to the control structure;

determining a difference between the simulated component dimensions within the region and target component dimensions within the region;

determining whether the difference exceeds a predetermined tolerance threshold;

adjusting a simulation condition in response to determining the difference exceeds the predetermined tolerance threshold; and

repeating the simulating of the component dimensions within the region, the determining of the difference, and the determining of whether the difference exceeds the predetermined tolerance threshold in response to the adjusting of the simulation condition.

2. The computer-implemented method of claim 1, wherein the control structure is in the data set representing the chip, and wherein the simulating of the component dimensions is performed on a chip-by-chip basis.

3. The computer-implemented method of claim 1, wherein the simulating of the component dimensions includes reading target values from one of a target file or target control table.

4. The computer-implemented method of claim 3, wherein the simulating of the component dimensions is further performed using initial simulation conditions for a first chip simulation.

5. The computer-implemented method of claim 4, further comprising running optical proximity correction verification on an entire chip in response to the determining the difference does not exceed the predetermined tolerance threshold.

6. The computer-implemented method of claim 5, further comprising:

modifying the initial simulation condition for a subsequent chip simulation after the running of the optical proximity correction verification; and

simulating the component dimensions for the subsequent chip simulation using the modified initial simulation condition.

7. The computer-implemented method of claim 1, wherein the initial simulation condition includes at least one of dose or focus.

8. A computer system comprising:

at least one computing device configured to diagnose in-line critical dimension control adjustments in a lithographic process by performing actions comprising;

locating a control structure in a data set representing one of a chip or a kerf;

simulating component dimensions within a region proximate to the control structure;

determining a difference between the simulated component dimensions within the region and target component dimensions within the region;

determining whether the difference exceeds a predetermined tolerance threshold;

adjusting a simulation condition in response to determining the difference exceeds the predetermined tolerance threshold; and

repeating the simulating of the component dimensions within the region, the determining of the difference, and the determining of whether the difference exceeds the predetermined tolerance threshold in response to the adjusting of the simulation condition.

9. The computer system of claim 8, wherein the control structure is in the data set representing the chip, and wherein the simulating of the component dimensions is performed on a chip-by-chip basis.

10. The computer system of claim 8, wherein the simulating of the component dimensions includes reading target values from one of a target file or target control table.

11. The computer system of claim 10, wherein the simulating of the component dimensions is further performed using initial simulation conditions for a first chip simulation.

12. The computer system of claim 11, further comprising running optical proximity correction verification on an entire chip in response to the determining the difference does not exceed the predetermined tolerance threshold.

13. The computer system of claim 12, further comprising:

modifying the initial simulation condition for a subsequent chip simulation after the running of the optical proximity correction verification; and

simulating the component dimensions for the subsequent chip simulation using the modified initial simulation condition.

14. The computer system of claim 8, wherein the initial simulation condition includes at least one of dose or focus.

15. A computer program comprising program code embodied in at least one computer-readable storage medium, which when executed, enables a computer system to diagnose in-line critical dimension control adjustments in a lithographic process, the method comprising:

locating a control structure in a data set representing one of a chip or a kerf;

simulating component dimensions within a region proximate to the control structure;

determining a difference between the simulated component dimensions within the region and target component dimensions within the region;

determining whether the difference exceeds a predetermined tolerance threshold;

adjusting a simulation condition in response to determining the difference exceeds the predetermined tolerance threshold; and

repeating the simulating of the component dimensions within the region, the determining of the difference, and the determining of whether the difference exceeds the predetermined tolerance threshold in response to the adjusting of the simulation condition.

16. The computer program of claim 15, wherein the simulation condition includes at least one of dose or focus.

17. The computer program of claim 15, wherein the simulating of the component dimensions includes reading target values from one of a target file or target control table.

18. The computer program of claim 15, wherein the simulating of the component dimensions is further performed using an initial simulation condition for a first chip simulation.

19. The computer program of claim 18, further comprising running optical proximity correction verification on an entire chip in response to the determining the difference does not exceed the predetermined tolerance threshold.

20. The computer program of claim 18, further comprising:

modifying the initial simulation condition for a subsequent chip simulation after the running of the optical proximity correction verification; and

simulating the component dimensions for the subsequent chip simulation using the modified initial simulation condition.