CIRCUITRY TO SELECT, AT LEAST IN PART, AT LEAST ONE MEMORY

• US 20120191896A1
• Filed: 01/25/2011
• Published: 07/26/2012
• Est. Priority Date: 01/25/2011
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Fang, Zhen, Zhao, Li, Iyer, Ravishankar, Makineni, Srihari, Liao, Guangdeng
• Application Number:
  US13/013,104
• Publication Number:
  US 20120191896A1
• Time in Patent Office: Days
• US Class Current: 711/6
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An embodiment may include circuitry to select, at least in part, from a plurality of memories, at least one memory to store data. The memories may be associated with respective processor cores. The circuitry may select, at least in part, the at least one memory based at least in part upon whether the data is included in at least one page that spans multiple memory lines that is to be processed by at least one of the processor cores. If the data is included in the at least one page, the circuitry may select, at least in part, the at least one memory, such that the at least one memory is proximate to the at least one of the processor cores. Many alternatives, variations, and modifications are possible.

Claims

1. An apparatus comprising:

circuitry to select, at least in part, from a plurality of memories, at least one memory to store data, the plurality of memories being associated with respective processor cores, the circuitry being to select, at least in part, the at least one memory based at least in part upon whether the data is comprised in at least one page that spans multiple memory lines that is to be processed by at least one of the processor cores, and if the data is comprised in the at least one page, the circuitry being to select, at least in part, the at least one memory, such that the at least one memory is proximate to the at least one of the processor cores.

2. The apparatus of claim 1, wherein:

the at least one page is allocated, at least in part, one or more physical memory addresses by at least one process executed, at least in part, by one or more of the processor cores;

the one or more physical memory addresses are in a first physical memory region associated, at least in part, with one or more first data portions to be distributed to the memories based at least in part upon a page-by-page allocation;

the at least one process is to allocate, at least in part, a second physical memory region associated, at least in part, with one or more second data portions to be distributed to the memories based at least in part upon a memory line-by-memory line allocation; and

the circuitry is to select, at least in part, the at least one memory based at least in part upon the one or more physical addresses and in which of the physical memory regions the one or more physical memory addresses are located.

3. The apparatus of claim 2, wherein:

the at least one process is to allocate, at least in part, the one or more physical memory addresses in response, at least in part, to and contemporaneous with invocation of a memory allocation function call; and

the at least one process comprises at least one operating system kernel process.

4. The apparatus of claim 2, wherein:

the circuitry comprises;

first circuitry and second circuitry to concurrently generate, at least in part, respective values indicating, at least in part, the at least one memory, based at least in part upon the memory line-by-memory line allocation and the page-by-page allocation, respectively; and

selector circuitry to select one of the respective values based at least in part upon the one or more physical addresses and in which of the physical memory regions the one or more physical memory addresses are located.

5. The apparatus of claim 1, wherein:

the plurality of processor cores are communicatively coupled to each other via at least one network-on-chip;

the at least one page comprises, at least in part, at least one packet received, at least in part, by a network interface controller, the at least one packet including the data; and

the plurality of processor cores, the memories, and the network-on-chip are comprised in an integrated circuit chip.

6. The apparatus of claim 1, wherein:

the at least one memory is local to the at least one of the processor cores and also is remote from one or more others of the processor cores;

the at least one of the processor cores comprises multiple processor cores to execute respective application threads to utilize, at least in part, the at least one page; and

the at least one page is allocated, at least in part, by at least one virtual machine monitor process.

7. A method comprising:

selecting, at least in part, by circuitry, from a plurality of memories at least one memory to store data, the plurality of memories being associated with respective processor cores, the circuitry being to select, at least in part, the at least one memory based at least in part upon whether the data is comprised in at least one page that spans multiple memory lines that is to be processed by at least one of the processor cores, and if the data is comprised in the at least one page, the circuitry being to select, at least in part, the at least one memory, such that the at least one memory is proximate to the at least one of the processor cores.

8. The method of claim 7, wherein:

the at least one page is allocated, at least in part, one or more physical memory addresses by at least one process executed, at least in part, by one or more of the processor cores;

the one or more physical memory addresses are in a first physical memory region associated, at least in part, with one or more first data portions to be distributed to the memories based at least in part upon a page-by-page allocation;

the at least one process is to allocate, at least in part, a second physical memory region associated, at least in part, with one or more second data portions to be distributed to the memories based at least in part upon a memory line-by-memory line allocation; and

the circuitry is to select, at least in part, the at least one memory based at least in part upon the one or more physical addresses and in which of the physical memory regions the one or more physical memory addresses are located.

9. The method of claim 8, wherein:

the at least one process is to allocate, at least in part, the one or more physical memory addresses in response, at least in part, to and contemporaneous with invocation of a memory allocation function call; and

the at least one process comprises at least one operating system kernel process.

10. The method of claim 8, wherein:

the circuitry comprises;

first circuitry and second circuitry to concurrently generate, at least in part, respective values indicating, at least in part, the at least one memory, based at least in part upon the memory line-by-memory line allocation and the page-by-page allocation, respectively; and

selector circuitry to select one of the respective values based at least in part upon the one or more physical addresses and in which of the physical memory regions the one or more physical memory addresses are located.

11. The method of claim 7, wherein:

the plurality of processor cores are communicatively coupled to each other via at least one network-on-chip;

the at least one page comprises, at least in part, at least one packet received, at least in part, by a network interface controller, the at least one packet including the data; and

the plurality of processor cores, the memories, and the network-on-chip are comprised in an integrated circuit chip.

12. The method of claim 7, wherein:

the at least one memory is local to the at least one of the processor cores and also is remote from one or more others of the processor cores;

the at least one of the processor cores comprises multiple processor cores to execute respective application threads to utilize, at least in part, the at least one page; and

the at least one page is allocated, at least in part, by at least one virtual machine monitor process.

13. Computer-readable memory storing one or more instructions that when executed by a machine result in performance of operations comprising:

selecting, at least in part, by circuitry, from a plurality of memories at least one memory to store data, the plurality of memories being associated with respective processor cores, the circuitry being to select, at least in part, the at least one memory based at least in part upon whether the data is comprised in at least one page that spans multiple memory lines that is to be processed by at least one of the processor cores, and if the data is comprised in the at least one page, the circuitry being to select, at least in part, the at least one memory, such that the at least one memory is proximate to the at least one of the processor cores.

14. The computer-readable memory of claim 13, wherein:

the at least one page is allocated, at least in part, one or more physical memory addresses by at least one process executed, at least in part, by one or more of the processor cores;

the one or more physical memory addresses are in a first physical memory region associated, at least in part, with one or more first data portions to be distributed to the memories based at least in part upon a page-by-page allocation;

the at least one process is to allocate, at least in part, a second physical memory region associated, at least in part, with one or more second data portions to be distributed to the memories based at least in part upon a memory line-by-memory line allocation; and

the circuitry is to select, at least in part, the at least one memory based at least in part upon the one or more physical addresses and in which of the physical memory regions the one or more physical memory addresses are located.

15. The computer-readable memory of claim 14, wherein:

the at least one process is to allocate, at least in part, the one or more physical memory addresses in response, at least in part, to and contemporaneous with invocation of a memory allocation function call; and

the at least one process comprises at least one operating system kernel process.

16. The computer-readable memory of claim 14, wherein:

the circuitry comprises;

first circuitry and second circuitry to concurrently generate, at least in part, respective values indicating, at least in part, the at least one memory, based at least in part upon the memory line-by-memory line allocation and the page-by-page allocation, respectively; and

selector circuitry to select one of the respective values based at least in part upon the one or more physical addresses and in which of the physical memory regions the one or more physical memory addresses are located.

17. The computer-readable memory of claim 13, wherein:

the plurality of processor cores are communicatively coupled to each other via at least one network-on-chip;

the at least one page comprises, at least in part, at least one packet received, at least in part, by a network interface controller, the at least one packet including the data; and

the plurality of processor cores, the memories, and the network-on-chip are comprised in an integrated circuit chip.

18. The computer-readable memory of claim 13, wherein:

the at least one memory is local to the at least one of the processor cores and also is remote from one or more others of the processor cores;

the at least one of the processor cores comprises multiple processor cores to execute respective application threads to utilize, at least in part, the at least one page; and

the at least one page is allocated, at least in part, by at least one virtual machine monitor process.