MEMORY MANAGEMENT DEVICE

• US 20120191900A1
• Filed: 01/17/2012
• Published: 07/26/2012
• Est. Priority Date: 07/17/2009
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KUNIMATSU, Atsushi, NAKAI, Hiroto, OWA, Tsutomu, UNESAKI, Tsutomu, MIYAGAWA, Masaki, NOZUE, Hiroshi, KAWAGOME, Kazuhiro, SAKAMOTO, Hiroyuki, NISHINO, Reina, MAEDA, Kenichi, TAKADA, Mari
• Application Number:
  US13/351,582
• Publication Number:
  US 20120191900A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.

Claims

1. A memory management device that controls writing into and reading from a main memory comprising a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor, the memory management device comprising:

a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory; and

a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.

2. The memory management device according to claim 1, wherein the coloring information comprises an access frequency estimated based on the data characteristic of the write target data.

3. The memory management device according to claim 1, wherein the coloring information comprises a data life estimated based on the data characteristic of the write target data.

4. The memory management device according to claim 1, wherein the coloring information comprises importance estimated based on the data characteristic of the write target data.

5. The memory management device according to claim 1, wherein the coloring information further comprises an access count to the write target data.

6. The memory management device according to claim 1, wherein the coloring information comprises at least one of an access frequency, a data life, and importance estimated based on the data characteristic of the write target data.

7. The memory management device according to claim 2, wherein the nonvolatile semiconductor memory comprises a first region and a second region,

the writing management unit references the coloring information to write the write target data of which the access frequency is high estimated based on the data characteristic into the first region, and

the writing management unit references the coloring information to write the write target data of which the access frequency is low estimated based on the data characteristic into the second region.

8. The memory management device according to claim 1, further comprising a reading management unit that determines whether to cache read target data in the volatile semiconductor memory by referencing the coloring information of the read target data when the read target data is read from the nonvolatile semiconductor memory.

9. The memory management device according to claim 1, wherein the nonvolatile semiconductor memory is a NAND flash memory and the volatile semiconductor memory is a DRAM.

10. The memory management device according to claim 6, wherein the at least one of the access frequency, the data life, and the importance estimated based on the data characteristic of the write target data is determined based on at least one of a characteristic of a file in a file system of the write target data and a characteristic of a data type when a program in which the write target data is handled is executed.

11. The memory management device according to claim 6, wherein the at least one of the access frequency, the data life, and the importance estimated based on the data characteristic of the write target data is determined based on an extension of the write target data.

12. The memory management device according to claim 6, wherein the at least one of the access frequency, the data life, and the importance estimated based on the data characteristic of the write target data is determined based on an arrangement region of a kernel of the write target data.

13. The memory management device according to claim 5, wherein an access frequency to the write target data is calculated based on the access count to the write target data and

the writing management unit references the access frequency to determine a writing region in the nonvolatile semiconductor memory of the write target data.

14. The memory management device according to claim 13, further comprising a relocation unit that relocates data by referencing the access count or the access frequency of the data in the nonvolatile semiconductor memory and the volatile semiconductor memory.

15. The memory management device according to claim 6, wherein the nonvolatile semiconductor memory comprises a first region and a second region and the second region can store more multi-bit data than the first region,

the writing management unit references the coloring information,

writes the write target data of which the data life is short estimated based on the data characteristic into the volatile semiconductor memory,

writes the write target data of which the data life is long estimated based on the data characteristic and of which the importance is high estimated based on the data characteristic into the first region of the nonvolatile semiconductor memory, and

writes the write target data of which the data life is long estimated based on the data characteristic and of which the importance is low estimated based on the data characteristic into the second region of the nonvolatile semiconductor memory.

16. The memory management device according to claim 6, wherein the coloring information further comprises an access count to the write target data,

the nonvolatile semiconductor memory comprises a first region and a second region, and

the writing management unit references the access frequency calculated based on the access count to the write target data to determine the region into which the write target data is written from the first region or the second region.

17. The memory management device according to claim 1, wherein the writing management unit determines a writing region based on the coloring information and memory usage information comprising an erasure count for each predetermined region of the nonvolatile semiconductor memory so that an occurrence count of erasure processing for the nonvolatile semiconductor memory by wear leveling is suppressed.

18. An information processing device, comprising:

a processor;

a nonvolatile semiconductor memory and a volatile semiconductor memory used as a main memory; and

a memory management unit that controls writing into and reading from the nonvolatile semiconductor memory and the volatile semiconductor memory in response to a writing request and a reading request from the processor, wherein

the memory management unit, including;

a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory; and

a writing management unit that references the coloring information to determine a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.

19. The information processing device according to claim 18, wherein the coloring information comprising at least one of an access frequency, a data life, and importance estimated based on the data characteristic of the write target data.

20. The information processing device according to claim 18, wherein the memory management unit further comprises a reading management unit that determines whether to cache read target data in the volatile semiconductor memory by referencing the coloring information of the read target data when the read target data is read from the nonvolatile semiconductor memory.

21. The information processing device according to claim 18, wherein the coloring information further comprises an access count to the write target data and the access count is counted by a counter included in the processor.