EXPANDABLE ASYMMETRIC-CHANNEL MEMORY SYSTEM

• US 20120191921A1
• Filed: 10/04/2010
• Published: 07/26/2012
• Est. Priority Date: 12/14/2009
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Shaeffer, Ian, Vaidyanath, Arun, Mukherjee, Sanku
• Granted Patent: US 9,183,166 B2
• Time in Patent Office: Days
• US Class Current: 711/149
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

Claims

1. An integrated circuit device for use in a memory system comprising memory sockets, the integrated circuit device comprising:

an internal data path formed by a first number of internal signaling links;

a signaling interface having a second number of interface nodes to be coupled to respective external signaling links, the second number being greater than the first number; and

switch circuitry to switchably couple the internal data path to selected interface nodes of the signaling interface in accordance with occupancy of the memory sockets.

2. The integrated circuit device of claim 1 wherein the selected interface nodes of the signaling interface constitute one of a plurality of subsets of interface nodes within the signaling interface, and wherein the switch circuitry switchably couples the internal data path to each of the subsets of interface nodes in accordance with the occupancy.

3. The integrated circuit device of claim 1 further comprising an integrated circuit die on which the internal data path and switch circuitry are located, wherein the interface nodes comprise contacts disposed on the integrated circuit die to enable electrical connection of the integrated circuit die to the external signaling links.

4. The integrated circuit device of claim 1 wherein a first subset of the internal signaling links is permanently coupled to a first subset of the interface nodes, and wherein the switch circuitry comprises circuitry to switchably couple each internal signaling link of a second subset of the internal signaling links to a respective one of at least two interface nodes of a second subset of the interface nodes.

5. The integrated circuit device of claim 1 wherein the second number of interface nodes comprises a plurality of sets of interface nodes, each set to be coupled exclusively to a respective one of the memory sockets via a respective set of the external signaling links.

6. The integrated circuit device of claim 5 wherein the plurality of sets of interface nodes comprises a first set of interface nodes to be coupled exclusively to a first one of the memory sockets, the first set of interface nodes including more interface nodes than any other set of interface nodes comprised by the plurality of sets of interface nodes.

7. The integrated circuit device of claim 5 wherein the plurality of sets of interface nodes comprises a first set of interface nodes to be coupled exclusively to a first one of the memory sockets, the first set of interface nodes including at least twice as many interface nodes as any other set of interface nodes comprised by the plurality of sets of interface nodes.

8. The integrated circuit device of claim 1 wherein the second number of interface nodes comprises N interface nodes to be coupled exclusively to a first one of M memory sockets within the memory system, and wherein the second number is less than the product of M and N.

9. The integrated circuit device of claim 1 wherein the second number (N) of interface nodes is given by the expression:

N=L+L*(0.5*log₂M), in which ‘

L’

is the first number of internal signaling links, ‘

M’

is the number of memory sockets within the memory system, and ‘

*’

denotes multiplication.

10. The integrated circuit device of claim 1 wherein each of the memory sockets has a unique socket number (X) which is an integer in the range from 1 to the number of memory sockets (M) and wherein the second number of interface nodes comprises M groups of interface nodes each to be coupled to a respective one of the M memory sockets, and wherein the number of interface nodes within each of the M groups is given by the expression:

L/(2^{roundup(log2X)}), where ‘

L’

is the first number of internal signaling links, “

roundup( )”

is a function that rounds its argument up to the nearest integer, and ‘

/’

denotes a division operation.

11. The integrated circuit device of claim 1 wherein a first subset of the second number of interface nodes is to be coupled exclusively to a first one of the memory sockets and a second subset of the second number of interface nodes is to be coupled exclusively to a second one of the memory sockets, and wherein the first subset includes twice as many interface nodes as the second subset.

12. The integrated circuit device of claim 11 wherein a third subset of the second number of interface nodes is to be coupled exclusively to a third one of the memory sockets and a fourth subset of the second number of interface nodes is to be coupled exclusively to a fourth one of the memory sockets, and wherein the first subset includes four times as many interface nodes as the third subset, and the third subset includes the same number of interface nodes as the fourth subset.

13. The integrated circuit device of claim 11 wherein the first subset of the second number of interface nodes comprises the first number of interface nodes to enable each of the internal signaling links of the internal data path to be coupled to the first memory socket, and wherein the second subset of the second number of interface nodes comprises fewer than the first number of interface nodes to enable only a fraction of the internal signaling links of the internal data path to be coupled to the second memory socket.

14. The integrated circuit device of claim 1 further comprising a programmable register to store a switch-control value that indicates occupancy of the memory sockets and to output the switch-control value to the switch circuitry.

15. The integrated circuit device of claim 1 further comprising a central processing unit.

16. The integrated circuit device of claim 1 wherein the signaling interface comprises a memory interface to receive signals from and to output signals to one or more occupied ones of the memory sockets, the integrated circuit device further comprising a control interface to receive signals from and output signals to an external memory controller circuit.

17. A method of operation within an integrated circuit device, the method comprising:

switchably coupling an internal signaling path to selected interface nodes of a signaling interface in accordance with occupancy of memory sockets within a memory system; and

transferring signals between the internal signaling path and the selected interface nodes.

18. The method of claim 17 wherein the internal signaling path comprises a first number of internal signaling links and the signaling interface comprises a second number of interface nodes coupled to external signaling links, the second number being greater than the first number, and wherein the selected interface nodes constitute a subset of interface nodes within the second number of interface nodes.

19. The method of claim 18 wherein the subset of interface nodes comprises the first number of interface nodes.

20. The method of claim 17 further comprising programming a switch-control value within a programmable register of the integrated-circuit device, wherein the switch-control value is indicative of the occupancy.

21. The method of claim 17 further comprising receiving a memory access request and wherein transferring signals between the internal signaling path and the selected interface nodes comprises transferring data signals between the internal signaling path and the selected interface nodes in response to the memory access request.

22. The method of claim 17 wherein the integrated circuit device is a buffer integrated circuit device comprising a controller interface coupled to a memory controller and wherein the signaling interface comprises at least part of a memory interface coupled to one or more of the memory sockets.

23. An assembly comprising:

a substrate;

data signaling lines disposed on one or more layers of the substrate; and

memory sockets mounted to the substrate and coupled to respective subsets of the data signaling lines, wherein the number of data signaling lines in the subset of data signaling lines coupled to a first one of the memory sockets is at least twice the number of data signaling lines in the subset of data signaling lines coupled to a second one of the memory sockets.

24. The assembly of claim 23 wherein the memory sockets are memory module sockets that permit removable insertion of memory modules.

25. The assembly of claim 23 further comprising command signaling lines coupled in common to each of the memory sockets.

26. The assembly of claim 23 wherein the data signaling lines constitute first data signaling lines and wherein the assembly further comprises:

second data signaling lines fewer in number than the first data signaling lines; and

conductive elements coupled between the second data signaling lines and a selected subset of the first data signaling lines.

27. The assembly of claim 23 wherein the conductive elements are switchable elements to permit the selected subset of the first signaling lines to be switched to a different subset of the first signaling lines.

28. An integrated circuit device for use in a memory system comprising memory sockets, the integrated circuit device comprising:

an internal data path formed by a first number of internal signaling links;

a signaling interface having a second number of interface nodes to be coupled to respective external signaling links, the second number being greater than the first number; and

means for switchably coupling the internal data path to selected interface nodes of the signaling interface in accordance with occupancy of the memory sockets.