DYNAMIC PROTOCOL FOR COMMUNICATING COMMAND AND ADDRESS INFORMATION
First Claim
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1. A memory device, comprising:
- a memory core including a plurality of memory cells; and
an interface circuit to receive a memory operation command that specifies a memory operation pertaining to an access of the memory core, wherein the memory operation command is specified in a packet that includes the memory operation command multiplexed with address information corresponding to the access; and
wherein a framing position marking the start of the packet is adjusted based at least on one prior received packet, received by the interface circuit.
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Abstract
A dynamic serialized command and address (CA) protocol with cycle-accurate matching between the PHY interface and the DFI interface is described. This CA protocol facilitates the use of a common memory-controller control logic with different CA bus configurations. With this CA protocol, CA packets for different memory operations have different formats. The size and the position of the CA packets vary relative to boundaries of DFI clock cycles, and the CA packets can extend beyond DFI clock cycle boundaries. In addition, there are at least two possible formats for a read or write memory operation. The appropriate format is selected based on the immediately preceding memory operation.
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Citations
23 Claims
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1. A memory device, comprising:
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a memory core including a plurality of memory cells; and an interface circuit to receive a memory operation command that specifies a memory operation pertaining to an access of the memory core, wherein the memory operation command is specified in a packet that includes the memory operation command multiplexed with address information corresponding to the access; and wherein a framing position marking the start of the packet is adjusted based at least on one prior received packet, received by the interface circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory controller, comprising:
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an interface circuit to transmit a memory operation command that specifies an access to a memory core of a memory device; wherein the memory operation command is specified in a packet that includes the memory operation command multiplexed with address information corresponding to the access; and wherein a framing position marking the start of the packet is adjusted based at least on one prior transmitted packet transmitted by the interface circuit. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A memory device, comprising:
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means for receiving memory operation commands using a serialized control and address protocol; wherein a respective command is specified in a packet; wherein at least two received packets have different sizes; and wherein a framing position marking the beginning of a respective packet is dynamically adjusted based at least on one or more prior packets.
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20. A memory controller, comprising:
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means for transmitting memory operation commands using a serialized control and address protocol; wherein a respective command is specified in a packet; wherein at least two received packets have different sizes; and wherein a framing position marking the beginning of a respective packet is dynamically adjusted based at least on one or more prior packets.
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21. A system, comprising:
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a bus; a memory controller comprising a first interface circuit coupled to the bus and configured to transmit memory operation commands using a serialized control and address protocol; and a memory device comprising a second interface circuit coupled to the bus and configured to receive the memory operation commands; wherein a respective memory operation command is specified in a packet; wherein at least two received packets have different sizes; and wherein a framing position marking the beginning of a respective packet is adjusted based at least on one or more prior packets.
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22. A method for receiving information, comprising:
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receiving a signal that includes groups of bits formatted using a serialized control and address protocol as a packet; and extracting information associated with memory operations from the groups of bits; wherein, for a respective memory operation of the memory operations, there are at least two packet sizes; and wherein a framing position marking the beginning of a respective packet is adjusted based at least on one or more prior packets.
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23. A method for providing information, comprising:
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encoding information associated with memory operations into groups of bits using a serialized control and address protocol; and transmitting a signal that includes the groups of bits in a packet format; wherein, for a respective memory operation, there are at least two packet sizes; and wherein a framing position marking the beginning of a respective packet is adjusted based at least on one or more prior packets
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Specification