METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING OPTIMIZING C-STATE SELECTION UNDER VARIABLE WAKEUP RATES

• US 20120191995A1
• Filed: 12/28/2011
• Published: 07/26/2012
• Est. Priority Date: 12/30/2005
• Status: Active Grant

• Current Assignee: Alon Naveh, Eliezer Weissmann, Nadav Shulman, Ofer Nathan
• Original Assignee: Intel Corporation
• Inventors: Naveh, Alon, Weissmann, Eliezer, Shulman, Nadav, Nathan, Ofer
• Granted Patent: US 8,799,687 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3246 by software initiated power-off
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.

Claims

1. A processor to support energy conservation techniques, comprising:

a plurality of processing cores,

an uncore area, and

a power management unit,

wherein the power management unit to,

receive a request from an operating system, wherein the request includes a first power saving state into which the processor is to be placed,

demote the processor to a second power state, which is a shallower power saving state than the first power state if a low activity period of the processor overlaps with a burst of high interrupt rate, and

un-demote the processor to a third power saving state, which is a deeper power saving state than the first power saving state in response to determining that an interrupt rate is low,

wherein the power management unit to proactively transition the processor into deeper power saving states even in the absence of a wake-up interrupt from an operating system.

2. The processor of claim 1, wherein the power management unit to un-demote the processor to a fourth state power saving state, which is deeper than third power saving state if a sleep duration of the processor in the third power saving state exceeds a demotion threshold even without receiving an interrupt from an operating system.

3. The processor of claim 2, wherein the power management unit to,

track the sleep duration of the processor in the third power saving state, and

increase the rate of transition from one power saving state to an even deeper power saving state during the low interrupt period.

4. The processor of claim 3, wherein the power management unit to increase the rate of transition between one power saving state to an even deeper power state during a zero interrupt period.

5. The processor of claim 4, wherein the power management unit to increase the rate of transition from one power saving state to a shallower power saving state in response to an occurrence of high interrupt rate.

6. The processor of claim 5, the power management unit further comprises a demotion counter to track the sleep duration, wherein the power management unit to demote the processor to the shallower power saving state if the sleep duration of the processor in the second power state is less than the demotion threshold.

7. The processor of claim 6, wherein the power management unit to,

increment the demotion counter by a demotion delta value, wherein the demotion delta value represents a rate at which the demotion counter is incremented or decremented, and

reset the demotion counter to erase interrupts, which have occurred outside a window period.

8. A method to support energy conservation techniques in a processor, comprising:

receiving a request from an operating system, wherein the request includes a first power saving state into which the processor is to be placed,

demoting the processor to a second power state, which is a shallower power saving state than the first power state if a low activity period of the processor overlaps with a burst of high interrupt rate, and

un-demoting the processor to a third power saving state, which is a deeper power saving state than the first power saving state in response to determining that an interrupt rate is low,

wherein the power management unit to proactively transition the processor into deeper power saving states even in the absence of a wake-up interrupt from an operating system.

9. The method of claim 8 comprises un-demoting the processor to a fourth state power saving state, which is deeper than third power saving state if a sleep duration of the processor in the third power saving state exceeds a demotion threshold even without receiving an interrupt from an operating system.

10. The method of claim 9 comprises,

tracking the sleep duration of the processor in the third power saving state, and

increasing the rate of transition from one power saving state to an even deeper power saving state during the low interrupt period.

11. The method of claim 10 comprises increasing the rate of transition between one power saving state to an even deeper power state during a zero interrupt period.

12. The method of claim 11 comprises increasing the rate of transition from one power saving state to a shallower power saving state in response to er an occurrence of high interrupt rate.

13. The method of claim 12 comprises,

tracking the sleep duration, and

demoting the processor to the shallower power saving state if a sleep duration of the processor in the second power state is less than the demotion threshold.

14. The method of claim 13 comprises,

incrementing the demotion counter by a demotion delta value, wherein the demotion delta value represents a rate at which the demotion counter is incremented or decremented, and

resetting the demotion counter to erase interrupts, which have occurred outside a window period.

15. A computer system to support energy conservation techniques, comprising:

a plurality of input-output devices,

a logic coupled to the plurality of input-output devices,

a display device coupled to the logic,

a machine readable storage medium coupled to the logic, and

a processor coupled to the logic, wherein the processor further includes,

a plurality of processing cores,

an uncore area, and

a power management unit, wherein the power management unit to, receive a request from an operating system, wherein the request

includes a first power saving state into which the processor is to be placed, demote the processor to a second power state, which is a shallower

power saving state than the first power state if a low activity period of the

processor overlaps with a burst of high interrupt rate, and

un-demote the processor to a third power saving state, which is a deeper power saving state than the first power saving state in response to determining that an interrupt rate is low,

wherein the power management unit to proactively transition the processor into deeper power saving states even in the absence of a wake-up interrupt from an operating system.

16. The computer system of claim 15, wherein the power management unit to un-demote the processor to a fourth state power saving state, which is deeper than third power saving state if a sleep duration of the processor in the third power saving state exceeds a demotion threshold even without receiving an interrupt from an operating system.

17. The computer system of claim 16, wherein the power management unit to,

track the sleep duration of the processor in the third power saving state, and

increase the rate of transition from one power saving state to an even deeper power saving state during the low interrupt period.

18. The computer system of claim 17, wherein the power management unit to increase the rate of transition between one power saving state to an even deeper power state during a zero interrupt period.

19. The computer system of claim 18, wherein the power management unit to increase the rate of transition from one power saving state to a shallower power saving state in response to an occurrence of high interrupt rate.

20. The computer system of claim 19, the power management unit further comprises a demotion counter to track the sleep duration, wherein the power management unit to,

demote the processor to the shallower power saving state if the sleep duration of the processor in the second power state is less than the demotion threshold,

increment the demotion counter by a demotion delta value, wherein the demotion delta value represents a rate at which the demotion counter is incremented or decremented, and

reset the demotion counter to erase interrupts, which have occurred outside a window period.