METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING OPTIMIZING C-STATE SELECTION UNDER VARIABLE WAKEUP RATES
First Claim
1. A processor to support energy conservation techniques, comprising:
- a plurality of processing cores,an uncore area, anda power management unit,wherein the power management unit to,receive a request from an operating system, wherein the request includes a first power saving state into which the processor is to be placed,demote the processor to a second power state, which is a shallower power saving state than the first power state if a low activity period of the processor overlaps with a burst of high interrupt rate, andun-demote the processor to a third power saving state, which is a deeper power saving state than the first power saving state in response to determining that an interrupt rate is low,wherein the power management unit to proactively transition the processor into deeper power saving states even in the absence of a wake-up interrupt from an operating system.
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Abstract
A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.
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Citations
20 Claims
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1. A processor to support energy conservation techniques, comprising:
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a plurality of processing cores, an uncore area, and a power management unit, wherein the power management unit to, receive a request from an operating system, wherein the request includes a first power saving state into which the processor is to be placed, demote the processor to a second power state, which is a shallower power saving state than the first power state if a low activity period of the processor overlaps with a burst of high interrupt rate, and un-demote the processor to a third power saving state, which is a deeper power saving state than the first power saving state in response to determining that an interrupt rate is low, wherein the power management unit to proactively transition the processor into deeper power saving states even in the absence of a wake-up interrupt from an operating system. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method to support energy conservation techniques in a processor, comprising:
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receiving a request from an operating system, wherein the request includes a first power saving state into which the processor is to be placed, demoting the processor to a second power state, which is a shallower power saving state than the first power state if a low activity period of the processor overlaps with a burst of high interrupt rate, and un-demoting the processor to a third power saving state, which is a deeper power saving state than the first power saving state in response to determining that an interrupt rate is low, wherein the power management unit to proactively transition the processor into deeper power saving states even in the absence of a wake-up interrupt from an operating system. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A computer system to support energy conservation techniques, comprising:
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a plurality of input-output devices, a logic coupled to the plurality of input-output devices, a display device coupled to the logic, a machine readable storage medium coupled to the logic, and a processor coupled to the logic, wherein the processor further includes, a plurality of processing cores, an uncore area, and a power management unit, wherein the power management unit to, receive a request from an operating system, wherein the request includes a first power saving state into which the processor is to be placed, demote the processor to a second power state, which is a shallower power saving state than the first power state if a low activity period of the processor overlaps with a burst of high interrupt rate, and un-demote the processor to a third power saving state, which is a deeper power saving state than the first power saving state in response to determining that an interrupt rate is low, wherein the power management unit to proactively transition the processor into deeper power saving states even in the absence of a wake-up interrupt from an operating system. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification