SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

• US 20120193779A1
• Filed: 07/01/2011
• Published: 08/02/2012
• Est. Priority Date: 01/28/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Chung-Sun, Kim, Jung-Hwan, Min, Tae-Hong, Song, Hyun-Jung, Youn, Sun-Pil
• Granted Patent: US 8,604,615 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1094 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip. The molding material may be on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile, the molding material is separated from sidewalls of the second chip by the homogeneous integral underfill material such that the molding material does not contact sidewalls of the second chip.

Claims

1. A stack of semiconductor chips comprising:

a first chip of the stack;

a second chip of the stack over the first chip;

conductive bumps extending between an upper surface of the first chip and a lower surface of the second chip;

a homogeneous integral underfill material interposed between the first chip and the second chip, encapsulating the conductive bumps, and extending along sidewalls of the second chip, the homogeneous integral underfill material having an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip; and

a molding material on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile, the molding material is separated from sidewalls of the second chip by the homogeneous integral underfill material such that the molding material does not contact sidewalls of the second chip.

2. The stack of claim 1, wherein the homogeneous integral underfill material comprises a combination of silica and resin.

3. The stack of claim 1, wherein the molding material completely surrounds all sides of the second chip.

4. The stack of claim 1, wherein the first chip comprises an integrated circuit and a plurality of through vias.

5. The stack of claim 4, wherein the second chip is electrically connected to some of the through vias

6. The stack of claim 5, wherein some of the through vias electrically connected to the second chip are isolated from the integrated circuit of the first chip.

8. The stack of claim 1, wherein the second chip is the topmost chip of the stack of semiconductor chips.

9. The semiconductor package of claim 1, wherein the upper surface of the underfill material is planar.

10. The semiconductor package of claim 1, wherein the upper surface of the underfill material has a cross sectional profile that is concave or convex.

11. The stack of claim 1, wherein an upper surface of the molding material, an upper surface of the homogeneous integral underfill material and the upper surface of the second chip are co-planar.

12. The stack of claim 1, wherein the entire upper surface of the molding material, the entire upper surface of the homogeneous integral underfill material and the entire upper surface of the second chip each lie within 5 um of a first plane.

13. The stack of claim 1, wherein the homogeneous integral underfill material extends above sidewalls of the second chip and contacts the upper surface of the second chip at locations adjacent the sidewalls.

14. The stack of claim 1, wherein the molding material extends over the upper surface of the second chip and contacts a center portion of the upper surface of the second chip.

15. The stack of claim 1, wherein the thickness of the first chip is 50 um or more and the thickness of the second chip is 50 um or less.

16. The stack of claim 1, wherein the coefficient of thermal expansion (CTE) of the stack is less than 6 ppm/K.

17. The stack of claim 16, wherein the CTE of the chip stack is less than 4 ppm/K.

18. The stack of claim 1, wherein a ratio of the CTE of the homogeneous integral underfill material to the CTE of the second chip is less than 1/3.

19. The stack of claim 1, wherein a CTE of the homogeneous integral underfill material is larger than a CTE of the first chip and smaller than a CTE of the molding material.

20. The stack of claim 1, wherein a ratio of the volume of molding material to the volume of the homogeneous integral underfill material is equal to or less than 2.

21. The stack of claim 1, wherein, with respect to a vertical cross sectional profile of the combination of the first chip, the second chip and the homogeneous integral underfill:

the homogeneous integral underfill material extends along the upper surface of the first chip a first distance from a first location directly under a first sidewall of the second chip to a second location at an edge of the underfill at the upper surface of the first chip that is not under the second chip, and

the homogeneous integral underfill material comprises an upper surface extending away from the first sidewall a second distance,

wherein a ratio of the second distance to the first distance less than or equal to 0.5.

22. The stack of claim 1, wherein a maximum thickness of the homogeneous integral underfill material in the horizontal direction from the sidewalls of the first chip is 700 μ

m.

23. The stack of claim 1, wherein a distance of an upper surface of the homogeneous integral underfill material in the horizontal direction from a sidewall of the second chip is different from a distance of the upper surface of the homogeneous integral underfill material in the horizontal direction from another sidewall of the second semiconductor chip.

24. The stack of claim 1, further comprising:

a heat sink attached to the backside of the second semiconductor chip.

25. The semiconductor device of claim 1, further comprising a package substrate disposed under the first chip.

26. The semiconductor device of claim 25, further comprising a filler covering a space between the package substrate and the first chip, sidewalls of the first chip, and part of sidewalls of the molding material.

27. The semiconductor device of claim 26, wherein a height from an upper surface of the package substrate to an upper surface of the molding portion is h, and a height from the upper surface of the package substrate to an upper surface of the filler is 0.7h or more.

7. The stack of 6, wherein others of the through vias are electrically connected to the integrated circuit of the first chip.

28. A stack of semiconductor chips comprising:

a first chip and a second chip over the first chip;

conductive bumps extending between an upper surface of the first chip and a lower surface of the second chip;

a homogeneous integral underfill material interposed between the first chip and the second chip, encapsulating the conductive bumps, and extending along sidewalls of the second chip to the upper surface of the second chip,

wherein the thickness of the first chip is 50 um or more and the thickness of the second chip is 50 um or less.

29. A stack of semiconductor chips comprising:

a first chip and a second chip over the first chip;

conductive bumps extending between an upper surface of the first chip and a lower surface of the second chip;

a homogeneous integral underfill material interposed between the first chip and the second chip, encapsulating the conductive bumps, and extending along sidewalls of the second chip to the upper surface of the second chip,

wherein the thickness from a lower surface of the first chip to the upper surface of the second chip is 120 um or less.

30. A method of manufacturing a semiconductor package device, comprising:

providing a substrate;

mounting a chip stack to the substrate, the chip stack comprising;

a first chip and a second chip over the first chip;

conductive bumps extending between an upper surface of the first chip and a lower surface of the second chip; and

a homogeneous integral underfill material interposed between the first chip and the second chip, encapsulating the conductive bumps, and extending along sidewalls of the second chip to the upper surface of the second chip,

wherein the coefficient of thermal expansion (CTE) of the chip stack is less than 6 ppm/K.

31. The method of claim 30, wherein the CTE of the chip stack is less than 4 ppm/K.

32. The method of claim 30, wherein the homogenous integral underfill material includes a first sub-underfill portion and a second sub-underfill portion, each portion comprising the same material.

33. The method of claim 32, wherein the first sub-underfill portion and second sub-underfill portion are formed at different times.

34. The method of claim 30, wherein a ratio of the CTE of the homogeneous integral underfill material and the CTE of the second chip is less than 1/3.

35. The method of claim 30, wherein a ratio of the CTE of the homogeneous integral underfill material and the CTE of the second chip is less than 1/6.

36. A method of manufacturing a semiconductor package device, comprising:

providing a substrate;

mounting a chip stack to the substrate, the chip stack comprising;

a first chip and a second chip over the first chip;

conductive bumps extending between an upper surface of the first chip and a lower surface of the second chip;

a homogeneous integral underfill material interposed between the first chip and the second chip, encapsulating the conductive bumps, and extending along sidewalls of the second chip to the upper surface of the second chip; and

a molding material on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip,

wherein a ratio of the volume of molding material to the volume of the homogeneous integral underfill material is equal to or less than 2.

37. The method of claim 36, wherein the ratio of the volume of molding material to the volume of the homogeneous integral underfill material is equal to or less than 1.

38. A method of manufacturing a semiconductor device comprising:

mounting, in a face down configuration, a plurality of first semiconductor chips to an upper surface of a substrate at different locations on the substrate, including connecting chip pads of the first chips to first conductive vias formed in the substrate;

forming a molding material about the plurality of first semiconductor chips;

etching backsides of the first semiconductor chips while the chips remain mounted to the wafer; and

singulating the substrate after etching backsides of the first semiconductor chip to form a plurality of first combinations of a first semiconductor chip and substrate parts.

39. The method of claim 38, wherein the etching step is comprises chemical mechanical polishing.

40. The method of claim 38, wherein the substrate comprises a semiconductor wafer.

41. The method of claim 38, wherein the substrate is a glass substrate.

42. The method of claim 38, further comprising, after singulating the substrate, mounting at least a first combination of the plurality of combinations to a second chip.

43. The method of claim 38, further comprising, after singulating the substrate, mounting at least a first combination of the plurality of combinations to a semiconductor package substrate.

44. A stack of semiconductor chips comprising:

a first chip and a second chip over the first chip;

conductive bumps extending between an upper surface of the first chip and a lower surface of the second chip;

a homogeneous integral underfill material interposed between the first chip and the second chip, encapsulating the conductive bumps, and extending from an upper surface of the first chip, along sidewalls of the second chip to the upper surface of the second chip,

wherein, with respect to a vertical cross sectional profile of the combination of the first chip, the second chip, and the homogeneous integral underfill material;

the homogeneous integral underfill material extends a first distance along the upper surface of the first chip, the first distance from a first location directly under a first sidewall of the second chip to a second location at an edge of the underfill material at the upper surface of the first chip that is not under the second chip,

the homogeneous integral underfill material comprises an upper surface extending away from the first sidewall a second distance, and

a ratio of the second distance to the first distance less than or equal to 0.5.

45. The stack of claim 44, wherein a ratio of the second distance to the first distance less than or equal to 0.3.

46. The stack of claim 44, wherein a ratio of the second distance to the first distance less than or equal to 0.1.

47. The semiconductor package of claim 44, wherein the second chip is directly mounted on the first chip.

48. The semiconductor package of claim 44, wherein the homogeneous integral underfill material contacts the upper surface of the first chip.

49. A method of manufacture, comprising:

mounting at least a first semiconductor chip on a first die area of a wafer, the first die area including a first integrated circuit;

mounting at least a second semiconductor chip on a second die area of the wafer, the second die area including a second integrated circuit;

forming an underfill material under the first and second semiconductor chips and along and above the sides of the first and second semiconductor chips;

forming a molding material around the underfill material; and

etching the molding material and the underfill material to expose backsides of the first and second semiconductor chips.

50. The method of claim 49, wherein top surfaces of the molding material and underfill material and the backsides of the first and second semiconductor chips are at the same level.

51. The method of claim 50, wherein top surfaces of the molding material and underfill material and the backsides of the first and second semiconductor chips are coplanar.

52. The method of claim 49, wherein the etching step comprises performing a chemical mechanical polishing of the molding material and underfill material.

53. The method of claim 49, wherein the etching step comprises thinning the first and second chips.

54. The method of claim 49, wherein the etching step comprises grinding the backsides of the first and second semiconductor chips to thin the first and second semiconductor chips.

55. The method of claim 54, further comprising attaching a heat sink to the backsides of the first and second semiconductor chips.

56. The method of claim 49, further comprising attaching a heat sink to the backsides of the first and second semiconductor chips.

57. The method of claim 49, further comprising cutting the wafer to separate the first die including the first integrated circuit from the second die including the second integrated circuit.

58. A stack of semiconductor chips comprising:

a first chip of the stack;

a second chip of the stack over the first chip;

conductive bumps extending between a upper surface of the first chip and a lower surface of the second chip;

a homogeneous integral underfill material interposed between the first chip and the second chip, encapsulating the conductive bumps, and extending along sidewalls of the second chip, the homogeneous integral underfill material having a an uppermost surface at sidewalls of the second chip located within 5 um of a first plane in which an upper surface of the second chip lies; and

a molding material on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, the molding material being separated from sidewalls of the second chip by the homogeneous integral underfill material.

59. The stack of claim 58, wherein the entire upper surface of the molding material, the entire upper surface of the homogeneous integral underfill material and the entire upper surface of the second chip each lie within 5 um of the first plane.

60. The stack of claim 58, wherein the molding material does not contact sidewalls of the second chip.