MEMORY SYSTEMS WITH MEMORY CHIPS DOWN AND UP
First Claim
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1. A system comprising:
- a memory controller chip, memory chips on a first substrate, and a module connector; and
a first group of conductors to provide read data signals from at least some of the memory chips to the memory controller chip, and a second group of conductors to provide read data signals from the connector to the memory controller chip.
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Abstract
In some embodiments, a system includes a memory controller chip, memory chips on a first substrate, and a module connector. A first group of conductors is included to provide read data signals from at least some of the memory chips to the memory controller chip, and a second group of conductors to provide read data signals from the connector to the memory controller chip. The module connector may receive a continuity card or memory module. Other embodiments are described.
4 Citations
1 Claim
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1. A system comprising:
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a memory controller chip, memory chips on a first substrate, and a module connector; and a first group of conductors to provide read data signals from at least some of the memory chips to the memory controller chip, and a second group of conductors to provide read data signals from the connector to the memory controller chip.
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Specification
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Current AssigneeRandy B. Osborne
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Original AssigneeRandy B. Osborne
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InventorsOsborne, Randy B.
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current361/679.31
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CPC Class CodesG06F 13/1684 using multiple buses
