Semiconductor device

• US 20120195136A1
• Filed: 02/07/2011
• Published: 08/02/2012
• Est. Priority Date: 01/28/2011
• Status: Active Grant

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Yoko, Hideyuki
• Granted Patent: US 8,400,805 B2
• Time in Patent Office: Days
• US Class Current: 365/189.07
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 29/702 by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H01L 2224/16145 the bodies being stacked

Abstract

A semiconductor device according to the present invention includes plural controlled chips CC0 to CC7 that hold mutually different layer information, and a control chip IF that supplies in common layer address signals A13 to A15 and a command signal ICMD to the controlled chips. Each bit that constitutes the layer address signals A13 to A15 is transmitted via at least two through silicon vias that are connected in parallel for each controlled chip out of plural first through silicon vias. Each bit that constitutes the command signal ICMD is transmitted via one corresponding through silicon via that is selected by an output switching circuit and an input switching circuit. With this configuration, the layer address signals A13 to A15 reach the controlled chips earlier than the command signal ICMD.

Claims

1. A semiconductor device comprising:

a plurality of controlled chips each of which holds layer information different from each other, the controlled chips comparing a layer address signal with the layer information, activating a layer selection signal when the layer address signal matches the layer information, and performing operation according to a command signal when the layer selection signal is activated; and

a control chip supplying the layer address signal and the command signal to the controlled chips in common, wherein

the controlled chips and control chip are electrically connected to each other via a plurality of penetration electrodes,

information of each bit that constitutes the layer address signal is transmitted via at least two first penetration electrodes for each of the controlled chips, and

information of each bit that constitutes the command signal is transmitted via one penetration electrode that is selected by a selection signal out of a plurality of second penetration electrodes for each of the controlled chips.

2. The semiconductor device as claimed in claim 1, wherein

the control chip includes 1^st to n^th driver circuits (n is a natural number) each of which outputs corresponding bits of the command signal,

each of the controlled chips includes 1^st to n^th receiver circuits each of which receives corresponding bits of the command signal,

the second penetration electrodes includes 1^st to n+m^th penetration electrodes (m is a natural number),

the control chip includes an output switching circuit that selectively connects each of the 1^st to n^th driver circuits to different ones of the 1^st to n+m^th penetration electrodes by connecting an i^th driver circuit to one of i^th to i+m^th penetration electrodes (i is an integer of 1 to n), and

each of the controlled chips includes an input switching circuit that selectively connects each of the 1^st to n^th receiver circuits to different ones of the 1^st to n+m^th penetration electrodes by connecting an i^th receiver circuit to one of i^th to i+m^th penetration electrodes.

3. The semiconductor device as claimed in claim 1, wherein

the control chip further includes a first latch circuit that latches the layer address signal supplied from outside and a second latch circuit that latches the command signal supplied from outside,

the first latch circuit is a through latch type that latches and outputs data synchronously with one of active edges of a clock signal, and

the second latch circuit is an edge-trigger type that latches data synchronously with the one of the active edges of the clock signal and outputs latched data synchronously with other of the active edges of the clock signal.

4. The semiconductor device as claimed in claim 1, wherein

each of the controlled chips includes a plurality of comparing circuits that compare each bit of the layer address signal with each bit of the layer information,

each of the comparing circuits includes a clocked inverter that has a signal input node, an enable node, and a signal output node, and a transfer gate that has a signal input node, an enable node, and a signal output node,

one of a corresponding bit of the layer address signal and a corresponding bit of the layer information is supplied to the signal input node of the clocked inverter and the signal input node of the transfer gate,

other one of a corresponding bit of the layer address signal and a corresponding bit of the layer information is supplied to the enable node of the clocked inverter and the enable node of the transfer gate, and

the signal output node of the clocked inverter and the signal output node of the transfer gate are short-circuited.

5. The semiconductor device as claimed in claim 1, wherein

the controlled chips are core chips each having memory cell array,

the control chip is an interface chip that controls the core chips, and

number of bits of data that are simultaneously input and output between the core chips and the interface chip is larger than number of bits of data that are simultaneously input and output between the interface chip and outside.

6. A semiconductor device comprising:

a plurality of controlled chips that hold mutually different layer information; and

a control chip that supplies in common a layer address signal and a command signal to the controlled chips, wherein

each of the controlled chips includes a layer-address comparing circuit that activates a layer selection signal when the layer address signal and the layer information match each other, a latch circuit that takes in the command signal when the layer selection signal is activated, a control circuit that operates in response to the command signal that is taken into the latch circuit, a plurality of first penetration electrodes provided through a corresponding chip and transmit the layer address signal, a plurality of second penetration electrodes provided through a corresponding chip and transmit the command signal, and an input switching circuit that selects penetration electrodes to be used out of the second penetration electrodes,

the control chip includes an output switching circuit that selects penetration electrodes to be used out of the second penetration electrodes,

each bit that constitutes the layer address signal is transmitted via at least two penetration electrodes that are connected in parallel for each of the controlled chips out of the first penetration electrodes, and

each bit that constitutes the command signal is transmitted via one corresponding penetration electrode that is selected by the output switching circuit and the input switching circuit.

7. A semiconductor device comprising:

a first controlled chip holding first layer address information defined by first layer address bits, and including a plurality of first penetration electrodes;

a second controlled chip stacked with the first controlled chip, the second controlled chip holding second layer address information defined by second layer address bits, the second layer address information and the second layer address bits being different from the first layer address information and the first layer address bits, respectively, the second controlled chip including a plurality of second penetration electrodes each electrically coupled with a corresponding one of the first penetration electrodes; and

a control chip stacked with the second controlled chip, including a plurality of third penetration electrodes each electrically coupled with a corresponding one of the second penetration electrodes and a corresponding one of the first penetration electrodes, supplying third layer address information defined by third layer address bits to the first and second controlled chips, selecting the first controlled chip when the third layer address information matches the first address information and the second controlled chip when the third layer address information matches the second layer address information, and each of the third layer address bits being supplied to the first and second controlled chips via at least two of the third penetration electrodes.

8. The semiconductor device as claimed in claim 7, wherein the at least two of the third penetration electrodes are electrically coupled to corresponding at least two of the second penetration electrodes and corresponding at least two of the first penetration electrodes.

9. The semiconductor device as claimed in claim 7, wherein the control chip further supplies command information defined by command bits to the first and second controlled chips to control the selected one of the first and second controlled chips and each of the command bits is supplied to the first and second controlled chips via a corresponding one of the third penetration electrodes.

10. The semiconductor device as claimed in claim 9, wherein the control chip further includes a switching circuit to select the corresponding ones of the third penetration electrodes in specified number of the third penetration electrodes.