LOCAL SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME

• US 20120195146A1
• Filed: 01/30/2012
• Published: 08/02/2012
• Est. Priority Date: 02/01/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: JUN, In-Woo, JUNG, Won-Chang
• Granted Patent: US 8,644,101 B2
• Time in Patent Office: Days
• US Class Current: 365/203
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A local sense amplifier circuit in a semiconductor memory device, the local sense amplifier circuit including a local data sensing unit configured to amplify a voltage difference between a local input/output (I/O) line pair based on a local sensing enable signal to provide the amplified voltage difference to a global I/O line pair, the local I/O line pair including a first local I/O line and a second local I/O line, and a local I/O line control unit including a first capacitor and a second capacitor, the first capacitor increasing a voltage level of the first local I/O line based on the local sensing enable signal, the second capacitor increasing a voltage level of the second local I/O line based on the local sensing enable signal.

Claims

1. A local sense amplifier circuit in a semiconductor memory device, the local sense amplifier circuit comprising:

a local data sensing unit configured to amplify a voltage difference between a local input/output (I/O) line pair based on a local sensing enable signal to provide the amplified voltage difference to a global I/O line pair, the local I/O line pair including a first local I/O line and a second local I/O line; and

a local I/O line control unit including a first capacitor and a second capacitor, the first capacitor increasing a voltage level of the first local I/O line based on the local sensing enable signal, the second capacitor increasing a voltage level of the second local I/O line based on the local sensing enable signal.

2. The local sense amplifier circuit as claimed in claim 1, wherein the first capacitor is a first metal oxide semiconductor (MOS) transistor that includes a gate electrode connected to the first local I/O line, a first electrode receiving the local sensing enable signal, and a second electrode connected to the first electrode of the first MOS transistor, and wherein the second capacitor is a second MOS transistor that includes a gate electrode connected to the second local I/O line, a first electrode receiving the local sensing enable signal, and a second electrode connected to the first electrode of the second MOS transistor.

3. The local sense amplifier circuit as claimed in claim 1, wherein the first capacitor is a first MOS transistor that includes a gate electrode receiving the local sensing enable signal, a first electrode connected to the first local I/O line, and a second electrode connected to the first electrode of the first MOS transistor, and wherein the second capacitor is a second MOS transistor that includes a gate electrode receiving the local sensing enable signal, a first electrode connected to the second local I/O line, and a second electrode connected to the first electrode of the second MOS transistor.

4. The local sense amplifier circuit as claimed in claim 1, wherein the local I/O line control unit increases the voltage levels of the local I/O line pair when the local sensing enable signal is activated, and wherein the local data sensing unit amplifies the voltage difference between the local I/O line pair to provide the amplified voltage difference to the global I/O line pair when the local sensing enable signal is activated.

5. The local sense amplifier circuit as claimed in claim 1, wherein the local data sensing unit includes:

a sensing block connected to the local I/O line pair, and configured to sense the voltage difference between the local I/O line pair;

an output block configured to amplify the sensed voltage difference in response to the local sensing enable signal to provide the amplified voltage difference to the global I/O line pair; and

a sensing control block configured to control the sensing operation of the sensing block and the amplifying operation of the output block in response to a selection enable signal.

6. The local sense amplifier circuit as claimed in claim 5, wherein the sensing control block includes:

a first MOS transistor having a first electrode receiving a ground voltage, a gate electrode receiving the selection enable signal, and a second electrode connected to a control node.

7. The local sense amplifier circuit as claimed in claim 6, wherein the sensing block includes:

a second MOS transistor having a first electrode connected to the control node, a gate electrode connected to the first local I/O line, and a second electrode; and

a third MOS transistor having a first electrode connected to the control node, a gate electrode connected to the second local I/O line, and a second electrode.

8. The local sense amplifier circuit as claimed in claim 7, wherein the output block includes:

a fourth MOS transistor having a first electrode connected to the second electrode of the second MOS transistor, a gate electrode receiving the local sensing enable signal, and a second electrode connected to one of the global I/O line pair; and

a fifth MOS transistor having a first electrode connected to the second electrode of the third MOS transistor, a gate electrode receiving the local sensing enable signal, and a second electrode connected to another one of the global I/O line pair.

9. A semiconductor memory device, comprising:

a memory cell array connected to a bitline pair;

a bitline sense amplifier circuit configured to amplify a voltage difference between the bitline pair based on a bitline sensing enable signal;

a column selection circuit configured to provide the amplified voltage difference between the bitline pair to a local input/output (I/O) line pair in response to a column selection signal, the local I/O line pair including a first local I/O line and a second local I/O line;

a local sense amplifier circuit including a first capacitor and a second capacitor, and configured to amplify a voltage difference between the local I/O line pair based on a local sensing enable signal to provide the amplified voltage difference between the local I/O line pair to a global I/O line pair, the first capacitor increasing a voltage level of the first local I/O line based on the local sensing enable signal, the second capacitor increasing a voltage level of the second local I/O line based on the local sensing enable signal; and

an I/O sense amplifier circuit configured to amplify a voltage difference between the global I/O line pair to generate a sensing output signal.

10. The semiconductor memory device as claimed in claim 9, wherein the local sense amplifier circuit increases the voltage levels of the local I/O line pair when the semiconductor memory device reads out the data stored in the memory cell array.

11. The semiconductor memory device as claimed in claim 9, further comprising:

a local I/O line precharge control circuit configured to precharge the local I/O line pair based on a precharge control signal and a precharge voltage.

12. The semiconductor memory device as claimed in claim 11, wherein the local I/O line precharge control circuit includes:

a first metal oxide semiconductor (MOS) transistor having a first electrode connected to the first local I/O line, a gate electrode receiving the precharge control signal, and a second electrode connected to the second local I/O line;

a second MOS transistor having a first electrode connected to the first local I/O line, a gate electrode receiving the precharge control signal, and a second electrode receiving the precharge voltage; and

a third MOS transistor having a first electrode connected to the second electrode of the second MOS transistor, a gate electrode receiving the precharge control signal, and a second electrode connected to the second local I/O line.

13. The semiconductor memory device as claimed in claim 9, further comprising:

an I/O buffer configured to generate output data based on the sensing output signal.

14. The semiconductor memory device as claimed in claim 9, wherein the I/O sense amplifier circuit amplifies the voltage difference between the global I/O line pair with current mode or voltage mode.

15. An electronic device, comprising:

a processor;

a memory cell array coupled to the processor, the memory cell array including at least one memory cell connected to a bitline pair;

a bitline sense amplifier circuit configured to receive voltages of the bitline pair and provide amplified voltages to a local input/output (I/O) line pair, the local I/O line pair including a first local I/O line and a second local I/O line;

a local sense amplifier circuit including a first capacitor and a second capacitor, the local sense amplifier circuit being configured to amplify a voltage difference between the local I/O line pair based on a local sensing enable signal to provide the amplified voltage difference between the local I/O line pair to a global I/O line pair, the first capacitor increasing a voltage level of the first local I/O line based on the local sensing enable signal, the second capacitor increasing a voltage level of the second local I/O line based on the local sensing enable signal; and

an I/O sense amplifier circuit configured to amplify a voltage difference between the global I/O line pair to generate a sensing output signal.

16. The electronic device as claimed in claim 15, wherein:

the first capacitor is a first metal oxide semiconductor (MOS) transistor that includes a gate electrode connected to the first local I/O line, and includes a first electrode and a second electrode coupled together and receiving the local sensing enable signal, and

the second capacitor is a second MOS transistor that includes a gate electrode connected to the second local I/O line, the second I/O line having a complementary signal to that of the first I/O line, the second capacitor further including a first electrode and a second electrode coupled together, coupled to the first and second electrodes of the first MOS transistor, and receiving the local sensing enable signal.

17. The electronic device as claimed in claim 16, wherein the first and second MOS transistors are NMOS transistors, and the local sensing enable signal provides a positive voltage pulse, relative to an inactive state of the local sensing enable signal, to the first and second electrodes of the first and second NMOS transistors.