IMAGE PROCESSING APPARATUS AND METHOD FOR PERFORMING A DISCRETE COSINE TRANSFORM

• US 20120195516A1
• Filed: 01/30/2012
• Published: 08/02/2012
• Est. Priority Date: 02/01/2011
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: KIM, Young Hyun
• Granted Patent: US 8,693,796 B2
• Time in Patent Office: Days
• US Class Current: 382/250
• CPC Class Codes: G06F 17/147 Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform G06F17/145 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/625 using discrete cosine transform [DCT]

Abstract

An image processing apparatus and method providing a high speed pipeline structure having a low level of complexity is described. The image processing apparatus includes a memory configured to store a plurality of data in a plurality of memory locations, where an ordinally specified data is in a corresponding ordinal memory location.

Claims

1. An image processing apparatus comprising:

a memory configured to store a plurality of data in a plurality of memory locations, wherein an ordinally specified data is in a corresponding ordinal memory location; and

an arithmetic operation unit configured to receive data from the memory, and updating the memory with results of arithmetic operations performed on the at least one of the plurality of data,

wherein in a first stage the arithmetic operation unit is configured to update for use in a second stage;

a first memory location with a sum of first and eighth data, a second memory location with a sum of second and seventh data, a seventh memory location with a difference between the second and the seventh data, and an eighth memory location with a difference between the first and the eighth data.

2. The apparatus of claim 1, wherein in the second stage the arithmetic operation unit is configured to update for a third stage:

a third memory location with a sum of third and sixth data, a fourth memory location with a sum of fourth and fifth data, a fifth memory location with a difference between the fourth and the fifth data, and a sixth memory location with a difference between the third and the sixth data.

3. The apparatus of claim 2, wherein, at the third stage the arithmetic operation unit is configured to update for a fourth stage:

the fifth memory location with a sum of the fifth and the sixth data, the sixth memory location with a sum of the sixth and the seventh data, and the seventh memory location with a sum of the seventh and the eighth data.

4. The apparatus of claim 3, wherein at the fourth stage the arithmetic operation unit is configured to update for a fifth stage:

the first memory location with a sum of the first and the fourth data, the second memory location with a sum of the second and the third data, the third memory location with a difference of the second and the third data, the fourth memory location with a difference of the first and the fourth data, and a ninth memory location with a difference of the fifth and the seventh data, and starts multiplication of;

a second cosine constant with the fifth data, a first cosine constant with the sixth data, and a third cosine constant with the seventh data.

5. The apparatus of claim 4, wherein at the fifth stage the arithmetic operation unit is configured to update for a sixth stage:

the first memory location with a sum of the first and the second data, the third memory location with a sum of the third and the fourth data, the second memory location with a difference of the first and the second data, the fifth memory location with a product of the second cosine constant and the fifth data, the sixth memory location with a product of the first cosine constant and the sixth data, and seventh memory location with a product of the third cosine constant and the seventh data, and starts multiplication of a fourth cosine constant with the ninth data.

6. The apparatus of claim 5, wherein at the sixth stage the arithmetic operation unit is configured to update for a seventh stage:

the sixth memory location with a sum of the eighth and the sixth data, the eighth memory location with a difference of the eighth and the sixth data, the ninth memory location with a product of the fourth cosine constant with the ninth data, and starts multiplication of the first cosine constant with the third data.

7. The apparatus of claim 6, wherein at the seventh stage the arithmetic operation unit is configured to update for an eighth stage:

the fifth memory location with a sum of the fifth and the ninth data, the seventh memory location with a sum of the seventh and the ninth data, and the third memory location with a product of the first cosine constant with the third data.

8. The apparatus of claim 7, wherein at the eighth stage the arithmetic operation unit is configured to update for use following the eighth stage:

the third memory location with a sum of the fourth and the third data, the fifth memory location with a sum of the eighth and the fifth data, the sixth memory location with a sum of the sixth and the seventh data, the fourth memory location with a difference of the fourth and the third data, the seventh memory location with a difference of the sixth and the seventh data, and the eighth memory location with a difference of the eighth and the fifth data.

9. The apparatus of claim 1, wherein the arithmetic operation unit comprises three addition units, three subtraction units, and four multiplication units.

10. The apparatus of claim 1, wherein the memory comprises first to ninth registers each storing first to ninth data.

11. The apparatus of claim 1, further comprising:

four level shifters converting one 16-bit data provided from the memory controller into two 8-bit data each having a range of −

128 to 127 to generate the first to eighth data used for the first stage; and

a memory input controller selecting data to be input to the memory from among outputs from the four level shifters, outputs from the arithmetic operation unit, and the data stored in the memory.

12. An image processing method comprising:

initializing first to eighth data, wherein each of the first to eighth data comprises a plurality of bits; and

updating in a first stage for use in a second stage;

the first data with a sum of the first and the eighth data, a second data with a sum of second and seventh data, a seventh data with a difference between the second and the seventh data, and an eighth data with a difference between the first and the eighth data.

13. The method of claim 12, comprising:

updating in the second stage for use in a third stage;

a third data with a sum of third and sixth data, a fourth data with a sum of fourth and fifth data, a fifth data with a difference between the fourth and the fifth data, and a sixth data with a difference between the third and the sixth data.

14. The method of claim 13, comprising:

updating in the third stage for use in a fourth stage;

the fifth data with a sum of the fifth and the sixth data, the sixth data with a sum of the sixth and the seventh data, and the seventh data with a sum of the seventh and the eighth data.

15. The method of claim 14, comprising:

updating in the fourth stage for use in a fifth stage;

the first data with a sum of the first and the fourth data, the second data with a sum of the second and the third data, the third data with a difference of the second and the third data, the fourth data with a difference of the first and the fourth data, and a ninth data with a difference of the fifth and the seventh data, and starts multiplication of;

a second cosine constant with the fifth data, a first cosine constant with the sixth data, and a third cosine constant with the seventh data.

16. The method of claim 15, comprising:

updating in the fifth stage for use in a sixth stage;

the first data with a sum of the first and the second data, the third data with a sum of the third and the fourth data, the second data with a difference of the first and the second data, the fifth data with a product of the second cosine constant and the fifth data, the sixth data with a product of the first cosine constant and the sixth data, and seventh data with a product of the third cosine constant and the seventh data, and starts multiplication of a fourth cosine constant with the ninth data.

17. The method of claim 16, comprising:

updating in the sixth stage for use in a seventh stage;

the sixth data with a sum of the eighth and the sixth data, the eighth data with a difference of the eighth and the sixth data, the ninth data with a product of the fourth cosine constant with the ninth data, and starts multiplication of the first cosine constant with the third data.

18. The method of claim 17, comprising:

updating in the seventh stage for use in an eighth stage;

the fifth data with a sum of the fifth and the ninth data, the seventh data with a sum of the seventh and the ninth data, and the third data with a product of the first cosine constant with the third data.

19. The method of claim 18, comprising:

updating in the eighth stage, for use after updating of the data used in the eighth stage;

the third data with a sum of the fourth and the third data, the fifth data with a sum of the eighth and the fifth data, the sixth data with a sum of the sixth and the seventh data, the fourth data with a difference of the fourth and the third data, the seventh data with a difference of the sixth and the seventh data, and the eighth data with a difference of the eighth and the fifth data; and

outputting the first to eighth data serially.