NON-BLOCKING, PIPELINED WRITE ALLOCATES WITH ALLOCATE DATA MERGING IN A MULTI-LEVEL CACHE SYSTEM

• US 20120198161A1
• Filed: 09/26/2011
• Published: 08/02/2012
• Est. Priority Date: 09/28/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chachad, Abhijeet Ashok, Damodaran, Raguram, Thompson, David Matthew
• Granted Patent: US 9,009,408 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/1652 in a multiprocessor architecture interprocessor communication using common memory G06F15/167
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/221 Static RAM
• CPC Class Codes: G06F 2212/2532 comprising a plurality of modules
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 9/3012 : Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: H03K 19/0016 : by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 21/00 : Details of pulse counters or frequency dividers
• CPC Class Codes: H03M 13/2903 : Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
• CPC Class Codes: H03M 13/353 : Adaptation to the channel
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 : in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

This invention handles write request cache misses. The cache controller stores write data, sends a read request to external memory for a corresponding cache line, merges the write data with data returned from the external memory and stores merged data in the cache. The cache controller includes buffers with plural entries storing the write address, the write data, the position of the write data within a cache line and unique identification number. This stored data enables the cache controller to proceed to servicing other access requests while waiting for response from the external memory.

Claims

1. A data processing system comprising:

a central processing unit executing program instructions to manipulate data;

a cache connected to said central processing unit temporarily storing in a plurality of cache lines data for manipulation by said central processing unit; and

a cache controller connected to said cache operation unit and said second level cache operable on a write request generating a cache miss to

store write data corresponding to said write request in a write data buffer,

send a read request to an external memory for a cache line of data encompassing said write request,

merge said write data stored in said write buffer with said cache line of data returned from the external memory in response to said read request, and

store said merged cache line of data in a corresponding cache line in said cache.

2. The data processing system of claim 1, wherein:

said cache controller is further operable to assign a unique identification number to said write request; and

wherein said cache controller includes

a command buffer including a plurality of entries, each entry storing a write address and a corresponding unique identification number, and

said write data buffer includes a plurality of entries, each entry storing write data and said corresponding unique identification number.

3. The data processing system of claim 2, wherein:

said cache controller is further operable to

match said data returned from the external memory with corresponding write data stored in an entry in said write data buffer using said unique identification number.

4. The data processing system of claim 3, wherein:

said cache controller further includes a response buffer having a plurality of entries, each entry storing a position of said write data within said cache line of data encompassing said write request and a corresponding unique identification number;

the external memory returns data in sequential portions less than all of said cache line of data encompassing said write request; and

said cache controller is further operable to

upon receipt of one of said sequential portions, determine if said sequential portion encompasses said write data from said position of said write data,

if said sequential portion does not encompasses said write data, store said sequential portion in a corresponding location within said cache, and

if said sequential portion encompasses said write data, merge said write data with said sequential portion and store said merged data in a corresponding location within said cache.

5. The data processing system of claim 4, wherein:

each entry of said response buffer storing an amount of data expected from the external memory in response to said read request; and

said cache controller is further operable to

following receipt of each of said sequential portions, determine if said sequential portion is a last sequential portion from said corresponding amount of data expected, and

release for reuse entries in said command buffer, said write data buffer and said response buffer identified by a corresponding unique identification number following storing data in said cache corresponding to said last sequential portion.

6. The data processing system of claim 2, wherein:

said cache controller id further operable to control plural write requests simultaneously.