Level One Data Cache Line Lock and Enhanced Snoop Protocol During Cache Victims and Writebacks to Maintain Level One Data Cache and Level Two Cache Coherence

• US 20120198163A1
• Filed: 09/28/2011
• Published: 08/02/2012
• Est. Priority Date: 09/28/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Damodaran, Raguram, Chachad, Abhijeet Ashok, Tran, Jonathan (Son) Hung, Thompson, David Matthew
• Granted Patent: US 9,003,122 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/1652 in a multiprocessor architecture interprocessor communication using common memory G06F15/167
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/221 Static RAM
• CPC Class Codes: G06F 2212/2532 comprising a plurality of modules
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 9/3012 : Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: H03K 19/0016 : by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 21/00 : Details of pulse counters or frequency dividers
• CPC Class Codes: H03M 13/2903 : Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
• CPC Class Codes: H03M 13/353 : Adaptation to the channel
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 : in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

This invention assures cache coherence in a multi-level cache system upon eviction of a higher level cache line. A victim buffer stored data on evicted lines. On a DMA access that may be cached in the higher level cache the lower level cache sends a snoop write. The address of this snoop write is compared with the victim buffer. On a hit in the victim buffer the write completes in the victim buffer. When the victim data passes to the next cache level it is written into a second victim buffer to be retired when the data is committed to cache. DMA write addresses are compared to addresses in this second victim buffer. On a match the write takes place in the second victim buffer. On a failure to match the controller sends a snoop write.

Claims

1. A data processing system comprising:

a central processing unit executing program instructions to manipulate data;

a first level data cache connected to said central processing unit temporarily storing in a plurality of cache lines data for manipulation by said central processing unit;

a second level memory connected to said first level cache including second level cache temporarily storing in a plurality of cache lines data for manipulation by said central processing unit and a second level local memory directly addressable by said central processing unit; and

a direct memory access unit connected to said central processing unit controlling data transfer, said direct memory access unit operating under control of said central processing unit to control data transfers including transferring data into said second level local memory;

a first level cache controller connected to said first level cache capable controlling data transfers into and out of said first level cache including

a first victim buffer having a plurality of entries, each entry storing an address corresponding to data stored in a cache line selected for replacement and said cache line, an entry initiated upon selection of a cache line for eviction and retired upon committing said cache line,

a snoop write port receiving write data and a corresponding address, and

a first victim comparator connected to said first victim buffer and said snoop write port comparing said address of each entry in said first victim buffer to said snoop write address,

said first level cache controller enabling a write of said snoop write data into a corresponding entry in said first victim buffer when said victim comparator detects a match between a snoop write address and a victim address in said victim buffer;

a second level memory controller connected to said first level cache operation unit and said second level cache controlling data transfers into and out of said second level cache, said second level cache including

a second victim buffer having a plurality of entries, each entry storing an address corresponding to data stored in said cache line selected for replacement and said cache line, an entry initiated upon receipt from said first level cache controller and upon storing said cache line to said second level memory,

a direct memory access write port receiving write data and a corresponding address of a direct memory access unit controlled data transfer, and

a second victim comparator connected to said second victim buffer and said direct memory access write port comparing said address of each entry in said second victim buffer to said direct memory access write address,

said second level memory controller enabling a write of said direct memory access write data into a corresponding entry in said second victim buffer if said second victim comparator detects a match between a direct memory access write address and a victim address in said second victim buffer and enabling a snoop write to said first level cache controller if said second victim comparator does not detect a match between a direct memory access write address and a victim address in said second victim buffer.

2. The data processing system of claim 1, wherein:

each cache line of said first level cache including a tag indicating a valid and a dirty status of said data stored therein;

said second level memory controller including a set of shadow tags corresponding to said tags of said first level data cache;

wherein said second level memory controller further includes a shadow tags comparator connected to said shadow tags and direct memory access write port comparing said address of each shadow tag to said direct memory access write address; and

wherein said second level memory controller enables a snoop write to said first level cache controller if said shadow tags comparator detects a match between a direct memory access write address and the address of one of said shadow tags.