APPARATUS AND METHOD FOR PROTECTING MEMORY IN MULTI-PROCESSOR SYSTEM

• US 20120198206A1
• Filed: 01/19/2012
• Published: 08/02/2012
• Est. Priority Date: 01/31/2011
• Status: Active Grant

• Current Assignee: Konkuk University Industrial Cooperation Corp, Samsung Electronics Co. Ltd.
• Original Assignee: Konkuk University Industrial Cooperation Corp, Samsung Electronics Co. Ltd.
• Inventors: Yoo, Jeong Joon, Lee, Seung Won, Lee, Shi Hwa, Im, Chae Seok, PARK, Jung Keun
• Granted Patent: US 9,135,187 B2
• Time in Patent Office: Days
• US Class Current: 711/206
• CPC Class Codes: G06F 12/1441 for a range

Abstract

Memory mapping in small units using a segment and subsegments is described, and thus it is possible to control a memory access even using a small amount of hardware, and it is possible to reduce costs incurred by hardware. Additionally, it is possible to prevent a memory from being destroyed due to a task error in the multi-processor system.

Claims

1. A memory protection method, comprising:

extracting a segment address and a subsegment address from a memory address corresponding to a memory access, when a Central Processing Unit (CPU) attempts the memory access with respect to a memory;

comparing the extracted segment address with a segment base address, and when the segment base address is different from the extracted segment address, transmitting an exception signal to the CPU, the segment base address being comprised in a segment register, and the exception signal indicating that the memory access is disallowed; and

determining whether the subsegment address is comprised in a subsegment register, and when the subsegment address is not comprised in the subsegment register, transmitting the exception signal to the CPU.

2. The memory protection method of claim 1, further comprising:

when the subsegment address is comprised in the subsegment register, determining whether the subsegment address is mapped, based on a map bit in the segment register, and when the subsegment address is unmapped, transmitting the exception signal to the CPU.

3. The memory protection method of claim 1, further comprising:

determining whether the memory access is allowed, based on a protection bit in the segment register, and when the memory access is disallowed, transmitting the exception signal to the CPU.

4. The memory protection method of claim 3, wherein the protection bit comprises information on an access right with respect to the memory.

5. A non-transitory computer readable recording medium storing a program to cause a computer to implement the method of claim 1.

6. A memory protection apparatus, comprising:

a subsegment register comprising a plurality of subsegment addresses;

a segment register comprising a segment base address; and

a Memory Protection Unit (MPU) to determine whether a memory access is allowed, based on the segment register and the subsegment register when a Central Processing Unit (CPU) attempts the memory access with respect to a memory, and to transmit an exception signal to the CPU when the memory access is disallowed, the exception signal indicating that the memory access is disallowed.

7. The memory protection apparatus of claim 6, wherein the MPU extracts a segment address from a memory address corresponding to the memory access, and compares the segment base address with the extracted segment address, and

when the segment base address is different from the extracted segment address, the MPU transmits the exception signal to the CPU.

8. The memory protection apparatus of claim 6, wherein the MPU extracts a subsegment address corresponding to the memory access from a memory address corresponding to the memory access, and determines whether the extracted subsegment address is comprised in the subsegment register, and

when the extracted subsegment address is not comprised in the subsegment register, the MPU transmits the exception signal to the CPU.

9. The memory protection apparatus of claim 8, wherein, when the extracted subsegment address is comprised in the subsegment register, the MPU determines whether the extracted subsegment address is mapped based on a map bit in the segment register, and

when the extracted subsegment address is unmapped, the MPU transmits the exception signal to the CPU.

10. The memory protection apparatus of claim 6, wherein the MPU determines whether the memory access is allowed, based on a protection bit in the segment register, and

when the memory access is disallowed, the MPU transmits the exception signal to the CPU.

11. A computer system comprising:

a memory protection apparatus, comprising;

an extractor to extract a segment address and a subsegment address from a memory address corresponding to a memory access;

a comparator to compare the extracted segment address with a segment base address; and

a transmitter to transmit an exception signal to a Central Processing Unit, if an exception condition exists.

12. The computer system of claim 11, wherein the exception signal is transmitted to indicate that memory access is disallowed.

13. The computer system of claim 11, wherein the exception condition exists if the segment base address is different from the extracted segment address.

14. The computer system of claim 11, wherein the exception condition exists if the subsegment address is not included in a subsegment register.