CONFIGURABLE SOURCE BASED/REQUESTOR BASED ERROR DETECTION AND CORRECTION FOR SOFT ERRORS IN MULTI-LEVEL CACHE MEMORY TO MINIMIZE CPU INTERRUPT SERVICE ROUTINES

• US 20120198310A1
• Filed: 09/23/2011
• Published: 08/02/2012
• Est. Priority Date: 09/28/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Tran, Jonathan (Son) Hung, Chachad, Abhijeet Ashok, Damodaran, Raguram, Gurram, Krishna Chaithanya
• Granted Patent: US 8,707,127 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/1652 in a multiprocessor architecture interprocessor communication using common memory G06F15/167
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/221 Static RAM
• CPC Class Codes: G06F 2212/2532 comprising a plurality of modules
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 9/3012 : Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: H03K 19/0016 : by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 21/00 : Details of pulse counters or frequency dividers
• CPC Class Codes: H03M 13/2903 : Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
• CPC Class Codes: H03M 13/353 : Adaptation to the channel
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 : in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

This invention is a memory system with parity generation which selectively forms and stores parity bits of corresponding plural data sources. The parity generation and storage depends upon the state of a global suspend bit and a global enable bit, and parity detection/correction corresponding to each data source.

Claims

1. A memory system comprising:

a plurality of data sources;

a memory for storing data;

a parity generator receiving data from said plurality of data sources operable to selectively form a set of parity bits corresponding to data from said plurality of data sources and store said data and corresponding parity bits in said memory.

2. The memory system of claim 1, further comprising:

a parity enable data register connected to said parity generator, said parity enable data register having a bit corresponding to each of said plurality of data sources; and

wherein said parity generator is operable to form parity bits and store said parity bits and said corresponding data in said memory if said bit of said parity bit enable register corresponding to said data source has a first digital state and store only said data in said memory if said bit of said parity bit enable register corresponding to said data source has a second digital state opposite to said first digital state.

3. The memory system of claim 1, further comprising:

an error detection status register having a suspend bit;

a parity enable data register connected to said parity generator, said parity enable data register having a bit corresponding to each of said plurality of data sources; and

wherein said parity generator is operable to store only said data in said memory if said suspend bit has a first digital state,

form parity bits and store said parity bits and said corresponding data in said memory if said bit of said parity bit enable register corresponding to said data source has a third digital state and said suspend bit has a second digital state opposite said first digital state, and

store only said data in said memory if said bit of said parity bit enable register corresponding to said data source has a fourth digital state opposite to said third digital state and said suspend bit has said second digital state.

4. The memory system of claim 1, wherein:

said memory includes a first memory bank and a second memory bank;

said plurality of data sources includes a first data source of N bits and a second data source having 2N bits;

said parity generator includes a first bank parity generator connected to receive N bits of said first data source, a second parity generator connected to receive N upper half bits of said second data source and a third parity generator connected to receive N lower half bits of said second data source;

a first multiplexer having a first input connected to said first parity generator receiving both said N bits and corresponding parity bits, a second input connected to said second parity generator receiving both said N upper half bits and corresponding parity bits and an output;

a second multiplexer having a first input connected to said first parity generator receiving both said N bits and corresponding parity bits, a second input connected to said third parity generator receiving both said N lower half bits and corresponding parity bits and an output;

wherein the memory system controls said first and second multiplexers to perform one of

select said first input as output of said first multiplexer and select no input as output of said second multiplexer thereby storing said N bits and said corresponding parity bits of said first data source in said first memory bank,

select no input as output of said first multiplexer and select said first input of said second multiplexer thereby storing said N bits of said first data source and said corresponding parity bits in said second memory bank, and

select said second input of said first multiplexer and select said second input of said second multiplexer thereby storing said N upper half bits of said second data source and said corresponding parity bits in said first memory bank and storing said N lower half bits of said second data source and said corresponding parity bits in said second memory bank.

5. The memory system of claim 1, further comprising:

a third data source having 2N bits;

said parity generator further including a fourth parity generator connected to receive N upper half of bits of said third data source and a fifth parity generator connected to receive N lower half of bits of said third data source;

said first multiplexer further having a third input connected to said fourth parity generator receiving both said N upper half bits and corresponding parity bits;

said second multiplexer further having a third input connected to said fifth parity generator receiving both said N lower half bits and corresponding parity bits;

wherein the memory system further controls said first and second multiplexers to

select said third input of said first multiplexer and select said third input of said second multiplexer thereby storing said N upper half bits of said third data source and said corresponding parity bits in said first memory bank and storing said N lower half bits of said third data source and said corresponding parity bits in said second memory bank.