CONFIGURABLE SOURCE BASED/REQUESTOR BASED ERROR DETECTION AND CORRECTION FOR SOFT ERRORS IN MULTI-LEVEL CACHE MEMORY TO MINIMIZE CPU INTERRUPT SERVICE ROUTINES
First Claim
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1. A memory system comprising:
- a plurality of data sources;
a memory for storing data;
a parity generator receiving data from said plurality of data sources operable to selectively form a set of parity bits corresponding to data from said plurality of data sources and store said data and corresponding parity bits in said memory.
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Abstract
This invention is a memory system with parity generation which selectively forms and stores parity bits of corresponding plural data sources. The parity generation and storage depends upon the state of a global suspend bit and a global enable bit, and parity detection/correction corresponding to each data source.
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Citations
5 Claims
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1. A memory system comprising:
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a plurality of data sources; a memory for storing data; a parity generator receiving data from said plurality of data sources operable to selectively form a set of parity bits corresponding to data from said plurality of data sources and store said data and corresponding parity bits in said memory. - View Dependent Claims (2, 3, 4, 5)
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Specification