METHOD OF READING AND WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY WITH ERROR CORRECTING CODE
First Claim
1. A method of reading states of bits in an ST-MRAM array, comprising:
- (a) reading data bits, ECC bits, and one or more inversion status bits from the ST-MRAM array;
(b) calculating a plurality of parity bits using one of an even or odd number of the data bits;
(c) generating corrected data bits and corrected ECC bits using the parity bits and ECC bits;
(d) storing the corrected data bits and corrected ECC bits if the inversion status bit is in a first state;
(e) inverting the corrected data bits if the inversion status bit is in a second state;
(f) storing the inverted corrected data bits and the corrected ECC bits if step (e) is accomplished and the parity bits are calculated using an even number of data bits;
(g) inverting the corrected ECC bits if the inversion status bit is in the second state and the parity bits are calculated using an odd number of data bits; and
(h) storing the inverted corrected data bits and the inverted corrected ECC bits if steps (e) and (g) are accomplished.
1 Assignment
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Accused Products
Abstract
A method includes destructively reading bits of a spin torque magnetic random access memory, using error correcting code (ECC) for error correction, and storing inverted or non-inverted data in data-store latches. When a subsequent write operation changes the state of data-store latches, parity calculation and majority detection of the bits are initiated. A majority bit detection and potential inversion of write data minimizes the number of write current pulses. A subsequent write operation received within a specified time or before an original write operation is commenced will cause the majority detection operation to abort.
32 Citations
20 Claims
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1. A method of reading states of bits in an ST-MRAM array, comprising:
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(a) reading data bits, ECC bits, and one or more inversion status bits from the ST-MRAM array; (b) calculating a plurality of parity bits using one of an even or odd number of the data bits; (c) generating corrected data bits and corrected ECC bits using the parity bits and ECC bits; (d) storing the corrected data bits and corrected ECC bits if the inversion status bit is in a first state; (e) inverting the corrected data bits if the inversion status bit is in a second state; (f) storing the inverted corrected data bits and the corrected ECC bits if step (e) is accomplished and the parity bits are calculated using an even number of data bits; (g) inverting the corrected ECC bits if the inversion status bit is in the second state and the parity bits are calculated using an odd number of data bits; and (h) storing the inverted corrected data bits and the inverted corrected ECC bits if steps (e) and (g) are accomplished. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of reading a plurality of bits in a row in a spin-torque magnetoresistive memory array, the method comprising:
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(a) reading a value of data bits, ECC bits, and inversion status bits in the spin-torque magnetoresistive memory array, the value being either a first state or a second state; (b) storing a value of each of the data bits, ECC bits, and inversion status bits in a plurality of latches; (c) setting the bits in the spin-torque magnetoresistive memory array to a first state; (d) calculating a plurality of parity bits using one of an even or odd number of the data bits; (e) generating corrected data bits and corrected ECC bits from the parity bits and ECC bits; (f) storing the corrected data bits and corrected ECC bits in the latches if the inversion status bit is in a first state; (g) inverting the corrected data bits if the inversion status bit is in a second state; (h) inverting the corrected ECC bits if the inversion status bit is in the second state and parity bits are calculated using an odd number of data bits; (i) storing the inverted corrected data bits and the corrected ECC bits in the latches if the inversion status bit is in the second state; and (j) writing either the stored data bits or an inversion of the stored data bits, and either the stored ECC bits or an inversion of the stored ECC bits, to the spin-torque magnetoresistive memory array as determined by whether the parity bits were calculated using an even number or an odd number of data bits. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A system of reading a plurality of bits in a spin torque magnetoresistive memory array containing data bits, ECC bits, and inversion status bits, the system comprising:
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a plurality of latches; and circuitry configured to; (a) read a value of data bits, ECC bits, and inversion status bits in the spin-torque magnetoresistive memory array, the value being either a first state or a second state; (b) store a value of each of the data bits, ECC bits, and inversion status bits in a plurality of latches; (c) calculate a plurality of parity bits using one of an even or odd number of the data bits; (d) generate corrected data bits and corrected ECC bits using the parity bits and ECC bits; (e) store the corrected data bits and corrected ECC bits in the latches if the inversion status bit is in a first state; (f) invert the corrected data bits if the inversion status bit is in a second state; (g) invert the corrected ECC bits if the inversion status bit is in the second state and the parity bits are calculated using an odd number of data bits; (h) store the inverted corrected data bits and the corrected ECC bits in the latches if the inversion status bit is in the second state; and (i) write either the stored data bits or an inversion of the stored data bits, and either the stored ECC bits or an inversion of the stored ECC bits, to the spin-torque magnetoresistive memory array as determined by whether the parity bits were calculated using an even number or an odd number of data bits.
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18. A system of reading a plurality of bits in a row in a spin-torque magnetoresistive memory array containing data bits, ECC bits, and inversion status bits, the system comprising:
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a triple modular redundancy evaluator coupled to the spin-torque magnetoresistive memory array and configured to; (a) receive the inversion status bits; (b) determine an inversion status bit using the majority state of the inversion status bits; (c) calculate inversion status output bits from an inversion status bit; and (d) provide the inversion status output bits to a plurality of data latches; a parity calculator coupled to the spin-torque magnetoresistive memory array and configured to; (e) receive the data bits; and (f) calculate parity bits using a plurality of data bits for each parity bit; an error corrector coupled to the spin-torque magnetoresistive memory array and the parity calculator and configured to; (g) receive the data bits and the ECC bits from the spin-torque magnetoresistive memory array; (h) receive the parity bits from the parity calculator; and (i) provide the ECC bits to the latches; and a data inversion unit coupled to the error corrector and the triple modular redundancy evaluator, and configured to; (j) receive corrected data bits from the error corrector and the inversion status bit from the triple modular redundancy evaluator, and (k) provide one of the corrected data bits or the inverted corrected data bits to the latches. - View Dependent Claims (19, 20)
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Specification