SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

• US 20120199891A1
• Filed: 10/04/2010
• Published: 08/09/2012
• Est. Priority Date: 10/09/2009
• Status: Abandoned Application

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Suzuki, Masahiko, Nishiki, Hirohiko, Chikama, Yoshimasa, Ohta, Yoshifumi, Aita, Tetsuya, Nakagawa, Okifumi, Hara, Takeshi
• Application Number:
  US13/499,960
• Publication Number:
  US 20120199891A1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A semiconductor device includes: a gate electrode (3) arranged on a substrate (1); a gate insulating layer (5) deposited over the gate electrode (3); an island of an oxide semiconductor layer (7) formed on the gate insulating layer (5) and including a channel region (7c) and first and second contact regions (7s, 7d) located on right- and left-hand sides of the channel region (7c); a source electrode (11) electrically connected to the first contact region (7s); a drain electrode (13) electrically connected to the second contact region (7d); and a protective layer (9) which is arranged on, and in contact with, the oxide semiconductor layer (7). The protective layer (9) covers the channel region (7c) on the surface of the oxide semiconductor layer (7), the sidewalls (7e) thereof located in a channel width direction with respect to the channel region (7c), and other portions (7f) thereof between the channel region (7c) and the sidewalls (7e). As a result, the hysteresis characteristic of a TFT that uses an oxide semiconductor can be improved and its reliability can be increased.

Claims

1. A semiconductor device comprising:

a substrate;

a gate electrode which is arranged on the substrate;

a gate insulating layer which has been deposited over the gate electrode;

an island of an oxide semiconductor layer which has been formed on the gate insulating layer and which includes a channel region and first and second contact regions that are located on right- and left-hand sides of the channel region;

a source electrode which is electrically connected to the first contact region;

a drain electrode which is electrically connected to the second contact region; and

a protective layer which is arranged on, and in contact with, the oxide semiconductor layer,

wherein the protective layer is a single layer and in contact with the channel region on the surface of the oxide semiconductor layer, the sidewalls of the oxide semiconductor layer that are located in a channel width direction with respect to the channel region, and other portions of the oxide semiconductor layer between the channel region and the sidewalls.

2. The semiconductor device of claim 1, wherein the protective layer is arranged between the oxide semiconductor layer and the source and drain electrodes and has a first hole that connects the source electrode to the first contact region and a second hole that connects the drain electrode to the second contact region.

3. The semiconductor device of claim 2, wherein the first and second holes partially overlap with the gate electrode.

4. The semiconductor device of claim 2, wherein the protective layer covers the upper surface and sidewalls of the surface of the oxide semiconductor layer entirely except the first and second contact regions.

5. The semiconductor device of claim 1, wherein when measured in a channel length direction, the width of the oxide semiconductor layer is greater than the width of the gate electrode.

6. The semiconductor device of claim 1, wherein at least the gate insulating layer and the oxide semiconductor layer are interposed between the upper surface and sidewalls of the gate electrode and the source electrode and between the upper surface and sidewalls of the gate electrode and the drain electrode.

7. The semiconductor device of claim 6, wherein the protective layer is further interposed between the upper surface and sidewalls of the gate electrode and the source electrode and between the upper surface and sidewalls of the gate electrode and the drain electrode.

9. The semiconductor device of claim 1, wherein the protective layer has a thickness of 50 nm to 200 nm.

10. The semiconductor device of claim 1, wherein the sidewalls of the oxide semiconductor layer that are located in a channel length direction with respect to the channel region are in contact with the source electrode or the drain electrode.

8. A method for fabricating a semiconductor device, the method comprising the steps of:

(A) forming a gate electrode on a substrate;

(B) forming a gate insulating layer so that the gate insulating layer covers the upper surface and sidewalls of the gate electrode;

(C) forming an island of an oxide semiconductor layer on the gate insulating layer;

(D) forming a protective layer on the oxide semiconductor layer so that the protective layer is in contact with the upper surface and sidewalls of the oxide semiconductor layer, the protective layer being a single layer;

(E) cutting first and second holes through the protective layer, thereby exposing two portions of the oxide semiconductor layer that are located on right- and left-hand sides of another portion thereof to be a channel region; and

(F) forming a source electrode that is electrically connected to the oxide semiconductor layer through the first hole and a drain electrode that is electrically connected to the oxide semiconductor layer through the second hole.