TRENCH MOS BARRIER SCHOTTKY (TMBS) HAVING MULTIPLE FLOATING GATES

• US 20120199902A1
• Filed: 02/04/2011
• Published: 08/09/2012
• Est. Priority Date: 02/04/2011
• Status: Active Grant

• Current Assignee: Vishay General Semiconductor LLC (Vishay Intertechnology Incorporated)
• Original Assignee: Vishay General Semiconductor LLC (Vishay Intertechnology Incorporated)
• Inventors: Kao, Lung-Ching
• Granted Patent: US 8,461,646 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A semiconductor rectifier is provided which includes a semiconductor substrate having a first type of conductivity. An epitaxial layer is formed on the substrate. The epitaxial layer has the first type of conductivity and is more lightly doped than the substrate. A plurality of floating gates is formed in the epitaxial layer and a metal layer is disposed over the epitaxial layer to form a Schottky contact therebetween. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.

Claims

1. A semiconductor rectifier, comprising:

a semiconductor substrate having a first type of conductivity;

an epitaxial layer formed on the substrate having the first type of conductivity and being more lightly doped than the substrate;

a plurality of floating gates formed in the epitaxial layer;

a metal layer disposed over the epitaxial layer to form a Schottky contact therebetween; and

a first electrode formed over the metal layer and a second electrode formed on a backside of the substrate.

2. The semiconductor rectifier of claim 1 wherein the plurality of floating gates are disposed in at least one trench formed in the epitaxial layer.

3. The semiconductor rectifier of claim 2 further comprising an insulating layer lining a bottom and sidewalls of the trench.

4. The semiconductor rectifier of claim 1 further comprising a plurality of dielectric layers disposed in the trench, wherein the plurality of floating gates includes a plurality of conducting layers each interposed between adjacent dielectric layers.

5. The semiconductor rectifier of claim 4 wherein the plurality of conducting layers is a plurality of Al layers.

6. The semiconductor rectifier of claim 4 wherein the plurality of conducting layers is a plurality of doped polysilicon layers.

7. The semiconductor rectifier of claim 1 wherein the metal layer is nickel and the epitaxial layer include silicon so that a silicide layer is formed at an interface between the nickel and epitaxial layers.

8. A method of fabricating a rectifier comprising:

providing a semiconductor body of a first conductivity type;

etching a plurality of trenches in a surface of the semiconductor body so that a mesa remains between adjacent trenches, each of the trenches having a sidewall and a bottom;

forming a plurality of floating gates in each of the trenches; and

forming a metal layer on a surface of the mesa so that a Schottky contact is formed therewith.

9. The method of claim 8 wherein the semiconductor body includes a semiconductor substrate having a first conductivity type and an epitaxial layer formed on the substrate having the first type of conductivity and being more lightly doped than the substrate.

10. The method of claim 8 wherein forming the plurality of floating gates in each of the trenches includes forming a plurality of alternating layers of a dielectric material and a conductive material in each of the trenches.

11. The method of claim 10 wherein forming each of the plurality of alternating layers includes depositing and etching back the dielectric material or the conductive material.

12. The method of claim 10 wherein the conductive material is Al.

13. The method of claim 10 wherein the conductive material is doped polysilicon.

14. The method of claim 8 wherein the metal layer is nickel and the epitaxial layer include silicon so that a silicide layer is formed at an interface between the nickel and epitaxial layers.