SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20120199904A1
• Filed: 01/26/2012
• Published: 08/09/2012
• Est. Priority Date: 02/03/2011
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: SASAKI, Kenji
• Application Number:
  US13/359,098
• Publication Number:
  US 20120199904A1
• Time in Patent Office: Days
• US Class Current: 257/343
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A field drain insulating part has a first insulating film and a high dielectric constant insulating film. The first insulating film is positioned at least in the center of the field drain insulating part in a plan view. The high dielectric constant insulating film is positioned at a part close to a drain region in the edge of the bottom surface of the field drain insulating part, and has a higher dielectric constant than the first insulating film. The high dielectric constant insulating film is not positioned in the center of the field drain insulating part in a plan view.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a first conductive type of a first conductive type well formed in the semiconductor substrate;

a second conductive type of a second conductive type well formed in the semiconductor substrate and formed adjacent to the first conductive type well;

a gate insulating film arranged over the semiconductor substrate across a part of the first conductive type well and a part of the second conductive type well;

a gate electrode arranged over the gate insulating film;

the second conductive type of a second impurity region formed over a surface layer of the first conductive type well;

the second conductive type of a first impurity region formed over a surface layer of the second conductive type well and formed apart from the gate electrode in a plan view; and

a field drain insulating part in which at least a part of the field drain insulating part is formed under the gate insulating film and which is formed over a surface of the second conductive type well between under the gate insulating film and the first impurity region,

wherein the field drain insulating part comprises;

a first insulating film positioned at least in a center part of the field drain insulating part in a plan view; and

a high dielectric constant insulating film arranged at least at a region close to the first impurity region in an edge of a bottom surface of the field drain insulating part and having a higher dielectric constant than the first insulating film.

2. The semiconductor device according to claim 1,

wherein the high dielectric constant insulating film is not arranged in the center part of the bottom surface of the field drain insulating part.

3. The semiconductor device according to claim 1,

wherein the first impurity region is a drain region.

4. The semiconductor device according to claim 1,

wherein the high dielectric constant insulating film is also formed at the second impurity region side in the edge of the bottom surface of the field drain insulating part.

5. The semiconductor device according to claim 4,

wherein the high dielectric constant insulating film is formed along the edge around the entire circumference of the bottom surface of the field drain insulating part.

6. The semiconductor device according to claim 1,

wherein the bottom surface of the field drain insulating part is polygon and,

wherein the high dielectric constant insulating film is formed at one side of the bottom surface close to the first impurity region in a plan view.

7. The semiconductor device according to claim 6,

wherein the high dielectric constant insulating film is also formed at one side of the bottom surface close to the second impurity region in a plan view.

8. The semiconductor device according to claim 1,

wherein a width of the high dielectric constant insulating film is 10% or more and 40% or less of a width of the field drain insulating part in a direction intersecting at right angles to an orientation direction of the gate electrode.

9. The semiconductor device according to claim 1,

wherein the substrate is a silicon substrate, and

wherein the field drain insulating part is embedded in a groove formed in the substrate, and

wherein a silicon dioxide film is formed over a bottom surface and side surfaces of the groove.

10. The semiconductor device according to claim 1,

wherein the first insulating film is a silicon dioxide film, and

wherein the high dielectric constant insulating film is at least one of silicon nitride film, a hafnium oxide film, tantalum oxide, titanium oxide, yttrium oxide, niobium pentoxide and zirconium oxide.

11. The semiconductor device according to claim 1,

wherein the gate insulating film, the gate electrode, the first impurity region, the second impurity region and the field drain insulating part configure a transistor, and

wherein the semiconductor device comprises an element separation film separating the transistor from other regions, and

wherein the element separation film is formed by the first insulating film and does not comprise the high dielectric constant insulating film.

12. A method for manufacturing a semiconductor device, the method comprising the steps of:

forming a groove in a semiconductor substrate;

forming a field drain insulating part by embedding an insulating film into the groove;

forming a gate insulating film and a gate electrode over the semiconductor substrate; and

forming a first impurity region and a second impurity region in a position facing each other through the gate electrode in a plan view,

wherein the semiconductor substrate has a first conductive type of a first conductive type well and a second conductive type of a second conductive type well adjacent to the first conductive type well, and

wherein the gate insulating film is arranged over the semiconductor substrate across a part of the first conductive type well and a part of the second conductive type well, and

wherein the second impurity region is the second conductive type and is formed over a surface layer of the first conductive type well, and

wherein the first impurity region is the second conductive type and is formed over a surface layer of the second conductive type well and is formed apart from the gate electrode in a plan view, and

wherein at least a part of the field drain insulating part is formed under the gate insulating film and the field drain insulating part is formed over the surface layer of the second conductive type well between under the gate insulating film and the first impurity region, and

wherein the step of forming a field drain insulating part includes the steps of;

forming a high dielectric constant film in the groove;

etching back the high dielectric constant film, and

thereby forming the high dielectric constant film at least at a part facing to the first impurity region in the edge of the bottom surface of the groove.

13. The method for manufacturing the semiconductor device according to claim 12, further comprising:

a step of embedding a first insulating film having a lower dielectric constant than the dielectric constant film into a remaining part of the groove, after the step of forming the high dielectric constant film,

14. The method for manufacturing the semiconductor device according to claim 12, the substrate being a silicon substrate, the method further comprising:

a step of forming a silicon dioxide film over the bottom surface and the side surfaces of the groove between the steps of forming the groove and forming the field drain insulating part.

15. The method for manufacturing the semiconductor device according to claim 12,

wherein the gate insulating film, the gate electrode, the first impurity region, the second impurity region and the field drain insulating part configure a transistor, and

wherein the method comprises a step of embedding an element separation film separating the transistor from other regions, before the step of forming the groove.