SEMICONDUCTOR DEVICE INCLUDING ANTIFUSE ELEMENT

• US 20120199943A1
• Filed: 04/16/2012
• Published: 08/09/2012
• Est. Priority Date: 08/24/2007
• Status: Abandoned Application

• Current Assignee: PS4 Luxco S.a.r.l.
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: OGAWA, Sumio
• Application Number:
  US13/448,096
• Publication Number:
  US 20120199943A1
• Time in Patent Office: Days
• US Class Current: 257/530
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An element isolation region exists at a side opposite to a diffusion layer region as seen from a channel region, without another electrode to which the same potential as one applied to the diffusion layer region is applied interposed between the channel region and the element isolation region. The electric field applied to the gate insulating film is not uniform and the magnitude of the electric field is increased when approaching closer to the diffusion layer region. Therefore, breakdown is likely to occur at parts closer to the diffusion layer region.

Claims

1. A semiconductor device having an antifuse element, the antifuse element comprising:

a first semiconductor region of a first conductivity type;

a diffusion region of a second conductivity type formed in the first semiconductor region, the diffusion region being electrically connected to a first electrode via a contact electrode, the diffusion region having a predetermined edge of non-linear shaped so as to form a concave portion;

a second semiconductor region of the second conductivity type electrically connected to the diffusion region, the second semiconductor region and the diffusion region being in a conductive state, and the second semiconductor region being in contact with the predetermined edge of the diffusion region;

an insulating film formed on the second semiconductor region; and

a second electrode formed on the insulating film to cover the second semiconductor region,

wherein the antifuse element can be programmed by a dielectric breakdown of the insulating film by applying a voltage between the second semiconductor region via the first electrode and the second electrode.

2. The semiconductor device as claimed in claim 1, further comprising an element isolation region surrounding the antifuse element.

3. The semiconductor device as claimed in claim 2, wherein the second electrode is elongated on the element isolation region so that a part of the second electrode covers the element isolation region.

4. The semiconductor device as claimed in claim 2, wherein the element isolation region includes a predetermined portion closer to the second electrode than the diffusion region, an area between the predetermined portion of the element isolation region and the predetermined edge of the diffusion region is free from another diffusion region coupled to the first electrode independent from the diffusion region.

5. The semiconductor device as claimed in claim 1, wherein the diffusion region has a substantially rectangular shape, the predetermined edge being one of edges of the rectangular shape.

6. The semiconductor device as claimed in claim 1, wherein the second semiconductor region is smaller in area than the diffusion region.

7. A semiconductor device having an antifuse element, the antifuse element comprising:

a first semiconductor region of a first conductivity type;

a diffusion region of a second conductivity type formed in the first semiconductor region, the diffusion region being electrically connected to a first electrode via a contact electrode;

a second semiconductor region of the second conductivity type electrically connected to the diffusion region, the diffusion region and the second semiconductor region being arranged in a first direction;

an insulating film formed on the second semiconductor region; and

a second electrode formed on the insulating film, a first width of the second electrode in a second direction different from the first direction being narrower than a second width of the diffusion region between first and second edges thereof that crossing the second direction,

wherein the antifuse element can be programmed by a dielectric breakdown of the insulating film by applying a voltage between the second semiconductor region via the first electrode and the second electrode.

8. The semiconductor device as claimed in claim 7, further comprising an element isolation region surrounding the antifuse element.

9. The semiconductor device as claimed in claim 8, wherein the second electrode is elongated on the element isolation region so that a part of the second electrode covers the element isolation region.

10. The semiconductor device as claimed in claim 8, wherein the element isolation region includes a predetermined portion closer to the second electrode than the diffusion region, an area between the predetermined portion of the element isolation region and the predetermined edge of the diffusion region is free from another diffusion region coupled to the first electrode independent from the diffusion region.

11. The semiconductor device as claimed in claim 7, wherein the diffusion region has a predetermined edge of non-linear shaped so as to form a concave portion, the second semiconductor region being arranged at the concave portion.

12. The semiconductor device as claimed in claim 11, wherein the predetermined edge includes first and second portions extending in the first direction, the concave portion being arranged between the first and second portions.

13. The semiconductor device as claimed in claim 7, wherein the second semiconductor region is smaller in area than the diffusion region.

14. A. semiconductor device having an antifuse element, the antifuse element comprising:

a first semiconductor region of a first conductivity type;

a diffusion region of a second conductivity type formed in the first semiconductor region, the diffusion region being electrically connected to a first electrode via a contact electrode;

a second semiconductor region of the second conductivity type electrically connected to the diffusion region, the second semiconductor being in contact with the diffusion region;

an insulating film formed on the second semiconductor region; and

a second electrode formed on the insulating film, the second electrode having an edge aligned with an edge of the insulating film,

wherein the antifuse element can be programmed by a dielectric breakdown of the insulating film by applying a voltage between the second semiconductor region via the first electrode and the second electrode.

15. The semiconductor device as claimed in claim 14, further comprising an element isolation region surrounding the antifuse element.

16. The semiconductor device as claimed in claim 15, wherein the second electrode is elongated on the element isolation region so that a part of the second electrode covers the element isolation region.

17. The semiconductor device as claimed in claim 15, wherein the element isolation region includes a predetermined portion closer to the second electrode than the diffusion region, an area between the predetermined portion of the element isolation region and the predetermined edge of the diffusion region is free from another diffusion region coupled to the first electrode independent from the diffusion region.

18. The semiconductor device as claimed in claim 14, wherein the diffusion region has a predetermined edge of non-linear shaped so as to form a concave portion, the second semiconductor region being arranged at the concave portion.

19. The semiconductor device as claimed in claim 18, wherein the predetermined edge includes first and second portions extending in parallel, the concave portion being arranged between the first and second portions.

20. The semiconductor device as claimed in claim 14, wherein the second semiconductor region is smaller in area than the diffusion region.