CHARGE PUMP AND ACTIVE FILTER FOR A FEEDBACK CIRCUIT

• US 20120200327A1
• Filed: 02/03/2011
• Published: 08/09/2012
• Est. Priority Date: 02/03/2011
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sreekiran, Samala, Chettuvetty, Ramesh
• Granted Patent: US 8,558,592 B2
• Time in Patent Office: Days
• US Class Current: 327/157
• CPC Class Codes: H03L 7/0893 the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
• CPC Class Codes: H03L 7/0896 the current generators being controlled by differential up-down pulses
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence

Abstract

A circuit containing a pair of charge pumps and an active filter receives outputs of a phase frequency detector used in a phase locked loop. The charge pump is implemented using switches and resistors to reduce performance variations due to component mismatches. The loop filter includes a resistor and a capacitor coupled in series, the resistor and the capacitor determining a zero of the transfer function of the loop filter. The charge pump circuit simultaneously injects a first current pulse at a first node of the loop filter and a second current pulse at a second node formed by a junction of the resistor and the capacitor. The polarity of the first current pulse is the opposite of the polarity of the second current pulse. Multiplication of the capacitance of the capacitor is thereby achieved, enabling implementation of the loop filter in integrated circuit form.

Claims

1. A circuit comprising:

a first charge pump comprising a first pair of switches and a first pair of resistors, a junction of the resistors in the first pair of resistors forming a first node, wherein the first charge pump is operable to source a first current to the first node or to sink the first current from the first node by operation of the first pair of switches;

a second charge pump comprising a second pair of switches and a second pair of resistors, a junction of the resistors in the second pair of resistors forming a second node, wherein the second charge pump is operable to source a second current to the second node or to sink the second current from the second node by operation of the second pair of switches; and

a filter comprising an impedance and a first capacitor coupled in series between a third node and a fourth node of the filter, wherein a junction of the impedance and the capacitor forms a fifth node of the filter, wherein the first node is coupled to the third node and the second node is coupled to the fifth node.

2. The circuit of claim 1, wherein the first capacitor determines a zero of the transfer function of the filter.

3. The circuit of claim 2, wherein the second charge pump sinks the second current from the second node when the first charge pump sources the first current to the first node, and

wherein the second charge pump sources the second current to the second node when the first charge pump sinks the first current from the first node.

4. The circuit of claim 3, wherein the filter is an active filter and the impedance is provided by a first resistor, the circuit further comprising:

a second capacitor coupled between the third node and the fourth node, and in parallel with the series combination of the first resistor and the first capacitor, the second capacitor determining a pole of the transfer function of the active filter;

a common-mode voltage generator to generate a common-mode voltage; and

an operational amplifier (OPAMP),

wherein an inverting terminal of the OPAMP is coupled to the third node, a non-inverting terminal of the OPAMP is coupled to the common-mode voltage, and an output terminal of the OPAMP is coupled to the fourth node.

5. The circuit of claim 4, wherein the common-mode voltage is generated to have a value to enable provision of a DC bias voltage across the first capacitor and the second capacitor, wherein each of the first capacitor and the second capacitor is implemented as a metal oxide semiconductor (MOS) capacitor.

6. The circuit of claim 1, wherein the first pair of switches comprises a first switch and a second switch, the first pair of resistors comprises a second resistor and a third resistor, wherein the second pair of switches comprises a third switch and a fourth switch, the second pair of resistors comprises a fourth resistor and a fifth resistor,

wherein the first switch is coupled between a first constant reference potential and the second resistor,

wherein the second switch is coupled between a second constant reference potential and the third resistor,

wherein the third switch is coupled between the first constant reference potential and the fourth resistor, and

wherein the fifth switch is coupled between the second constant reference potential and the fifth resistor.

7. The circuit of claim 1, wherein switches in each of the first pair of switches and the second pair of switches are controlled to be ON or OFF by signals generated by a phase frequency detector.

8. A phase locked loop (PLL) in integrated circuit (IC) form, the PLL comprising:

a phase frequency detector (PFD) coupled to receive an input clock and a local clock as inputs, the PFD to generate a pair of error signals comprising a first error signal and a second error signal, wherein the pulse widths of the first error signal and the second error signal are proportional respectively to the extent of lead or lag between the input signal and the output signal;

a charge pump circuit to receive the first error signal and the second error signal, and to generate corresponding current pulses,

a loop filter to perform low-pass filtering of the current pulses to generate a low-pass filtered signal;

a voltage controlled oscillator (VCO) coupled to receive the low-pass filtered signal and to generate an output clock, the frequency of the output clock being proportional to the voltage level of the low-pass filtered signal; and

a frequency divider to divide the frequency of the output clock to generate the local clock,

wherein the loop filter comprises a first resistor and a first capacitor coupled in series, the first resistor and the first capacitor determining a zero of the transfer function of the loop filter,

wherein the charge pump circuit simultaneously injects a first current pulse at a first node of the loop filter and a second current pulse at a second node of the loop filter, wherein the second node is a junction of the first resistor and the first capacitor, and wherein the polarity of the first current pulse is the opposite of the polarity of the second current pulse.

9. The PLL of claim 8, wherein the charge pump circuit comprises a first switch, a second switch, a third switch, a fourth switch, a second resistor, a third resistor, a fourth resistor and a fifth resistor,

wherein the first switch is coupled between a first constant reference potential and the second resistor,

wherein the second switch is coupled between a second constant reference potential and the third resistor,

wherein the third switch is coupled between the first constant reference potential and the fourth resistor, and

wherein the fifth switch is coupled between the second constant reference potential and the fifth resistor.

10. The PLL of claim 9, wherein the loop filter is an active circuit, the loop filter further comprising:

a second capacitor coupled between the first node and a third node of the loop filter, the second capacitor being coupled in parallel with the series combination of the first resistor and the first capacitor, the second capacitor determining a pole of the transfer function of the active filter;

a common-mode voltage generator to generate a common-mode voltage; and

an operational amplifier (OPAMP),

wherein an inverting terminal of the OPAMP is coupled to the first node, a non-inverting terminal of the OPAMP is coupled to the common-mode voltage, and an output terminal of the OPAMP is coupled to the third node.

11. The PLL of claim 9, wherein the common-mode voltage is generated to have a value to enable provision of a DC bias voltage across the first capacitor and the second capacitor, wherein each of the first capacitor and the second capacitor is implemented as a metal oxide semiconductor (MOS) capacitor.