Dynamic Biasing Systems and Methods

• US 20120200338A1
• Filed: 02/04/2011
• Published: 08/09/2012
• Est. Priority Date: 02/04/2011
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Olson, Chris
• Granted Patent: US 8,330,504 B2
• Time in Patent Office: Days
• US Class Current: 327/534
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/145 in field-effect transistor switches

Abstract

Dynamic biasing methods and circuits are described. The described methods generate bias voltages that are continuously varied so as to control stress voltages across transistors used within a cascode stack.

Claims

1. A dynamic biasing method comprising:

capacitively coupling to a gate terminal of a first field-effect transistor, a first waveform that is generated at a drain terminal of the first field-effect transistor;

deriving a first feedback signal from the capacitively coupled waveform present at the gate terminal of the first field-effect transistor;

repetitively sampling the first feedback signal and generating therefrom, a first time-varying gate bias signal; and

combining the first time-varying gate bias signal with a first steady-state DC bias voltage to generate a first dynamic gate biasing signal that operates upon the first field-effect transistor for setting a first source-drain voltage in the first field-effect transistor.

2. The biasing method of claim 1, wherein the first field-effect transistor is coupled to a second field-effect transistor to form at least one of an upper or a lower leg of a cascode stack.

3. The biasing method of claim 2, further comprising:

capacitively coupling to a gate terminal of the second field-effect transistor, a second waveform that is generated at a drain terminal of the second field-effect transistor;

deriving a second feedback signal from the capacitively coupled waveform present at the gate terminal of the second field-effect transistor;

repetitively sampling the second feedback signal and generating therefrom, a second time-varying gate bias signal; and

combining the second time-varying gate bias signal with a second steady-state DC bias voltage to generate a second dynamic gate biasing signal that operates upon the second field-effect transistor for setting a second source-drain voltage in the second field-effect transistor.

4. The biasing method of claim 3, wherein the second source-drain voltage is set substantially equal to the first source-drain voltage.

5. The biasing method of claim 3, wherein the amplitudes of each of the first and the second source-drain voltages is determined at least in part by at least one of:

a) the number of field-effect transistors present in the at least one of the upper or the lower leg of the cascode stack, or b) a power supply voltage applied to the at least one of the upper or the lower leg of the cascode stack.

6. The biasing method of claim 2, further comprising:

using a first switch-control signal to control a third field-effect transistor that is configured to operate as a first switching element coupled in series with the first and the second field-effect transistors located in the at least one of the upper or the lower leg of the cascode stack.

7. The biasing method of claim 3, wherein the first field-effect transistor is further coupled to a third field-effect transistor, thereby forming a junction node wherein an output signal of the cascode stack is generated.

8. The biasing method of claim 7, wherein each of the first and the second field-effect transistor is a P-channel field-effect transistor and the third field-effect transistor is an N-channel field-effect transistor.

9. The biasing method of claim 8, further comprising:

capacitively coupling to a gate terminal of the third field-effect transistor, a third waveform that is generated at a drain terminal of the third field-effect transistor;

deriving a third feedback signal from the capacitively coupled waveform present at the gate terminal of the third field-effect transistor;

repetitively sampling the third feedback signal and generating therefrom, a third time-varying gate bias signal; and

combining the third time-varying gate bias signal with a third steady-state DC bias voltage to generate a third dynamic gate biasing signal that operates upon the third field-effect transistor for setting a first source-drain voltage in the third field-effect transistor.

10. The biasing method of claim 9, wherein each of the first and the third waveforms is the same as the output signal of the cascode stack, due to the coupling of the first field-effect transistor to the third field-effect transistor.

11. The biasing method of claim 3, wherein the first feedback signal is a first binary signal and generating the first time-varying gate bias signal comprises repetitively sampling the low amplitude levels of the first binary signal.

12. The biasing method of claim 11, wherein the second feedback signal is a second binary signal and generating the second time-varying gate bias signal comprises repetitively sampling the high amplitude levels of the second binary signal.

13. A dynamic bias circuit comprising:

a coupling capacitor located between a drain terminal and a gate terminal of a first field effect transistor for coupling to the gate terminal, a first waveform that is generated at the drain terminal of the first field-effect transistor;

a first resistor network configured for generating a first feedback signal from the capacitively coupled waveform present at the gate terminal of the first field-effect transistor;

a sampling circuit for repetitively sampling the first feedback signal and generating therefrom, a first time-varying gate bias signal;

a second resistor network configured for generating a first steady-state DC bias voltage; and

an operational amplifier circuit configured for combining the first time-varying gate bias signal with the first steady-state DC bias voltage to generate a first dynamic gate biasing signal that operates upon the first field-effect transistor for setting a first source-drain voltage in the first field-effect transistor.

14. The bias circuit of claim 14, wherein the first field-effect transistor is coupled to a second field-effect transistor to form at least one of an upper or a lower leg of a cascode stack.

15. The bias circuit of claim 14, further comprising a bypass capacitor which operates in conjunction with the coupling capacitor to form a capacitive divider network to provide to the gate terminal of the first field effect transistor, a fractional portion of the first waveform that is generated at the drain terminal of the first field-effect transistor.

16. The bias circuit of claim 14, wherein the first resistor network comprises a first plurality of resistors configured as a first resistive divider network, and the second resistor network comprises a second plurality of resistors configured as a second resistive divider network.

17. The bias circuit of claim 16, wherein the first resistive divider network is a part of the second resistive divider network.

18. The bias circuit of claim 14, wherein each of the first and the second field-effect transistors is part of an upper leg of the cascode stack, and wherein a third field-effect transistor is configured as a part of a lower leg of the cascode stack.

19. The bias circuit of claim 14, wherein the feedback signal is a binary signal, and the sampling circuit repetitively samples one of the low amplitude levels or the high amplitude levels of the first binary signal.

20. The bias circuit of claim 14, further comprising a start-up circuit coupled to the gate terminal of the first field-effect transistor, the start-up circuit configured to have a first time constant that is selected based on a second time constant associated with a power supply provided to the cascode stack.