Means and circuit to shorten the optical response time of liquid crystal displays

• US 20120200550A1
• Filed: 02/03/2011
• Published: 08/09/2012
• Est. Priority Date: 02/03/2011
• Status: Active Grant

• Current Assignee: Ernst Lueder
• Original Assignee: Ernst Lueder
• Inventors: Lueder, Ernst
• Granted Patent: US 8,928,643 B2
• Time in Patent Office: Days
• US Class Current: 345/211
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

A liquid crystal display with a plurality of picture elements arranged in a matrix of rows and columns has a voltage signal applied sequentially to the signal lines such that a first TFT at each pixel in a row is made conductive and driving voltages are applied to the data lines such that enlarged voltages V_a=k V_d with k>1 are applied sequentially to the input of the addressing circuit of each data line where V_d is the desired voltage for a given grey shade. A control circuit is utilized where signal processing takes place within the signal addressing circuit with the additional components of series connected capacitors C₁ and C₂ across the LC-pixel and an additional TFT across C₁ with the second TFT controlled by a gate signal fed from an external voltage source in order to establish the desired voltage V_d. An alternate configuration is a circuit for applying a voltage V_a and then V_d sequentially to the signal lines such that a first TFT at each pixel in a row of pixels is made conductive.

Claims

1. A liquid crystal display having a plurality of picture elements arranged in a matrix of rows and columns, the display having two opposed substrates, a common electrode on one substrate, and picture elements having driving electrodes on the opposing substrate said picture elements comprising:

a plurality of parallel and spaced apart data lines and substantially orthogonal signal lines insulated from each other and at each intersection a first driving electrode and an associated intermediate component means for coupling said data line and said corresponding first electrode all formed on the surface of said first substrate facing said second substrate, where

a voltage is applied sequentially to the signal lines such that a first TFT at each pixel in a row of pixels is made conductive and

driving voltages are applied to the data lines such that enlarged voltages V_a=k V_d with k>

1 are applied sequentially to the input of the addressing circuit of each data line where V_d is the desired voltage for a given grey shade and V_a is the enlarged voltage for the acceleration of the rotation of the LC-molecules.

4. A method for driving a liquid crystal display according to claim 1 such that the bounded but otherwise variable parameters k>

1 and t₀<

t_f are chosen so as to optimize the waveform of the voltage V_p across the pixel for shortening the response time while achieving the desired gray shade, but limited in such a way as to not cause excessive turbulence in the orientation of the LC-molecules.

6. A method for driving a liquid crystal display according to claim 1 such that the variable parameter k is determined in advance and then stays fixed, while the value of t₀<

T_f is selected during the operation of the LCD with the same value for all pixels in a row of pixels so as to improve on the LC response time for applied voltages V_d.

9. A liquid crystal control circuit according to claim 6 wherein the value of the resistor is chosen such that the high but decaying voltage across C₁ accelerates the rotation of the LC-molecules and reduces the voltage V_p across the pixel to values approaching the voltage V_d within the time T_f.

10. A liquid crystal display according to claim 1 where the first step of a 2-step method for driving a liquid crystal display is the application of the enlarged voltage V_a=kV_d with k>

1, at the input of the data lines as the signal line addressing circuits are sequentially activated.

12. A liquid crystal display control circuit according to claim 1 where the N rows are sub-divided into blocks with N_r rows where Σ

N_r=N. so that the blocks are addressed simultaneously and independently of each other so as to provide the enlarged voltages V_a.

13. A liquid crystal display control circuit according to claim 10 where the sub-divided blocks have about the same number of rows.

14. A method for driving a liquid crystal display according to claim 4 where the factor k is selected for each pixel in a row and for each addressing step differently so as to control the voltages V_a.

15. A method for driving a liquid crystal display according to claim 10 where the time t₀<

T_f for the beginning of the second step of the addressing method ends the higher voltage acceleration time and can be selected differently for each block and for each row in the blocks.

16. A method for driving a liquid crystal display according to claim 9 where the two step addressing method is performed in one-half the conventional addressing time for each step in order not to increase the total addressing time required.

2. A liquid crystal display device having a plurality of picture elements arranged in a matrix of columns and rows comprising:

a first substrate and a second substrate, said substrates facing each other and spaced apart for defining a space there between both said substrates with at least one of the substrates being transparent;

a plurality of parallel and spaced apart data lines and substantially orthogonal signal lines insulated from each other and at each intersection a first driving electrode and an associated intermediate component means for coupling said data line to said corresponding first electrode all formed on the surface of said first substrate facing said second substrate;

a circuit for applying a voltage sequentially to the signal lines such that a first TFT at each pixel in a row of pixels is made conductive and

a control circuit where signal processing takes place within the signal addressing circuit with the additional components of series connected capacitors C₁ and C₂ across the LC-pixel and an additional TFT across C₁, with the second TFT controlled by a gate signal fed from an external voltage source and,

a liquid crystal material filling the space between said substrates.

3. A method for driving a liquid crystal display according to claim 2 such that at the time t₀ less than the frame time T_f, the second TFT is rendered conductive via an external gate signal thereby discharging capacitor C₁ but not C₂ with the remaining voltage across C₂ being equal to V_d, the voltage required for the given grey shade.

5. A liquid crystal display device according to claim 2 such that the bounded but otherwise variable parameters k>

1 and t₀<

t_f are chosen so as to optimize the waveform of the voltage V_p across the pixel for shortening the response time while achieving the desired gray shade, but limited in such a way as to not cause excessive turbulence in the orientation of the LC-molecules.

7. A liquid crystal display device according to claim 2 such that the variable parameter k is determined in advance and then stays fixed, while the value of

t₀<

T_f is selected during the operation of the LCD with the same value for all pixels in a row of pixels so as to improve on the LC response time for applied voltages V_d

8. A liquid crystal control circuit according to claim 2 wherein the second TFT is replaced by a TFT with a short between the drain and gate so as to function as a resistor R.

11. A method for driving a liquid crystal display according to claim 8 wherein after step 1 having addressed all data lines of an LCD with the enlarged voltages V_a, at a second time interval less than T_f all data lines are consecutively addressed again starting with the first row in order to provide for each column the voltages V_d.