VIDEO SIGNAL PROCESSING CIRCUIT, VIDEO SIGNAL PROCESSING METHOD USED IN SAME, AND IMAGE DISPLAY DEVICE USING SAME

• US 20120200777A1
• Filed: 02/06/2012
• Published: 08/09/2012
• Est. Priority Date: 02/07/2011
• Status: Active Grant

• Current Assignee: NLT Technologies, Ltd. (Tianma Microelectronics Company Limited)
• Original Assignee: NLT Technologies, Ltd. (Tianma Microelectronics Company Limited)
• Inventors: OOGA, Kouichi
• Granted Patent: US 8,730,255 B2
• Time in Patent Office: Days
• US Class Current: 348/575
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2330/06 Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
• CPC Class Codes: G09G 2370/14 Use of low voltage differential signaling [LVDS] for display data communication
• CPC Class Codes: G09G 5/003 Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto specific for a CRT G09G1/165; for a flat panel G09G3/2092
• CPC Class Codes: H04N 5/21 Circuitry for suppressing or minimising disturbance, e.g. moiré or halo

Abstract

There is provided a video signal processing method for performing predetermined signal processing on an input video signal to transmit an output video signal in a form of a specified transmission format through a video signal line including invalid bit polarity setting processing to be performed by an invalid bit polarity setting unit, wherein, when there exists an invalid bit having no data corresponding to data making up the input video signal in the specified transmission format of the output video signal, to count the number of low and high levels of gray-level data of the input video signal to compare a numerical size between the number of low levels and the number of high levels for judgment and to set a polarity of the invalid bit based on the judgment result.

Claims

1. A video signal processing circuit for performing predetermined signal processing on an input video signal to transmit an output video signal in a form of a specified transmission format through a video signal line, comprising:

an invalid bit polarity setting unit, when there exists an invalid bit having no data corresponding to data making up said input video signal in the specified transmission format of said output video signal, to count a number of low and high levels of gray-level data of said input video signal, to compare a numerical size between said number of low levels and said number of high levels for judgment, and to set a polarity of said invalid bit based on a result of the judgment.

2. The video signal processing circuit according to claim 1, wherein said invalid bit polarity setting unit comprises:

an input video signal judging unit to count the number of low and high levels of said gray-level data of said input video signal and to compare a numerical size between said number of low levels and number of high levels for judgment to output a result of the judgment and,

an invalid bit polarity determining unit to determine a polarity of said invalid bit based on the result of the judgment obtained by said input video signal judging unit.

3. The video signal processing circuit according to claim 2,

wherein said input video signal judging unit is configured to count said number of low and high levels of said gray-level data of said input video signal existing within a period corresponding to a predetermined period in said output video signal in which said invalid bit exists, and

wherein said invalid bit polarity determining unit to determine a polarity of said invalid bit to be high level when said number of high levels is more than half of a total number and to determine a polarity of said invalid bit to be low level when said number of low levels is more than half of the total number.

4. The video signal processing circuit according to claim 3, wherein said invalid bit polarity determining unit is configured to determine a polarity of said invalid bit to be low level when said number of high levels is same as that of low levels.

17. An image display device having the video signal processing circuit as defined in claim 1.

5. A video signal processing circuit for performing predetermined signal processing on an input video signal to transmit an output video signal in a form of a specified transmission format through a video signal line, comprising:

an invalid bit polarity setting unit, when there exists an invalid bit having no data corresponding to data making up said input video signal in the specified transmission format of said output video signal, to set a polarity of said invalid bit existing in the specified transmission format of said output video signal to be same as a polarity of one valid data bit before valid data bit in terms of time series.

18. An image display device having the video signal processing circuit as defined in claim 5.

6. A video signal processing circuit for performing predetermined signal processing on an input video signal to transmit an output video signal in a form of a specified transmission format through a video signal line, which is configured as a master-side device to which a slave-side device having a plurality of data storing devices and an address is connected through said video signal line and which outputs said address and a signal demanding transmitting/receiving operations, in every determined period, to said slave-side device and transmits said output video signal or receives data from said slave-side device and also outputs device selection bit data for selection of each of said data storing devices of said slave-side device at time of transmitting mode and which has an invalid bit polarity setting unit, at time of receiving mode during which each of said data storing devices of said slave-side device is not selected, to count said number of low and high levels of said data received from said slave-side device in every predetermined period and to compare a numerical size between said number of low levels and number of high levels for judgment to set a polarity of said device selection bit data which becomes invalid data based on a result of the judgment.

7. The video signal processing circuit according to claim 6, wherein said invalid bit polarity unit comprises a transmission mode judging device to judge, in every predetermined period, whether said video signal processing circuit is in a transmission mode or in a receiving mode, based on the transmitting/receiving demand, a counting device to count said number of low and high levels of said data received from said slave-side device when said transmission mode is judged by said transmission mode judging device to be the receiving mode, and an invalid bit polarity determining unit to compare a numerical size between said number of low and high levels of said data counted by said counting device is compared for judgment in every predetermined period and to determine a polarity of said invalid bit based on the result of the judgment.

8. The video signal processing unit according to claim 7, wherein said invalid bit polarity determining unit is configured to determine a polarity of said invalid bit to be high level when said number of high levels is more than half of a total number and to determine a polarity of said invalid bit to be low level when said number of low levels is more than half of the total number.

9. The video signal processing unit according to claim 8, wherein said invalid bit polarity determining unit is configured to determine said invalid bit to be low level when said number of high level is same as that of low level.

19. An image display device having the video signal processing circuit as defined in claim 6.

10. A video signal processing circuit for performing predetermined signal processing on an input video signal to transmit an output video signal in a form of a specified transmission format through a video signal line, which is configured as a master-side device to which a slave-side device having a plurality of data storing devices and an address is connected through said video signal line and which outputs said address and a signal demanding transmitting/receiving operations, in every determined period, to said slave-side device and transmits said output video signal or receives data from said slave-side device and also outputs device selection bit data for selection of each of said data storing devices of said slave-side device at time of transmitting mode and which comprises an invalid bit polarity setting unit to set a polarity of said device selection bit data which becomes an invalid bit at time of receiving mode during which each of said data storing devices of said slave-side devices is not selected, to be same as a polarity of one valid data bit before valid data bit in terms of time series.

20. An image display device having the video signal processing circuit as defined in claim 10.

11. A video signal processing method for performing predetermined signal processing on an input video signal to transmit an output video signal in a form of a specified transmission format through a video signal line comprising:

invalid bit polarity setting processing to be performed by an invalid bit polarity setting unit, wherein, when there exists an invalid bit having no data corresponding to data making up said input video signal in the specified transmission format of said output video signal, to count a number of low and high levels of gray-level data of said input video signal, to compare a numerical size between said number of low levels and said number of high levels for judgment, and to set a polarity of said invalid bit based on a result of the judgment.

12. The video signal processing method according to claim 11, wherein, in said invalid bit polarity setting processing, an input video signal judging unit performs an input video signal judging process of counting said number of low levels and high levels of gray-level data of said input video signal and comparing a numerical size between said number of low levels and high levels for judgment and outputting a result of the judgment and an invalid bit polarity determining unit performs an invalid bit polarity determining process of determining a polarity of said invalid bit based on the result of the judgment obtained by said input video signal judging unit.

13. A video signal processing method to be used in a circuit performing predetermined signal processing on an input video signal to transmit an output video signal in a form of a specified transmission format through a video signal line, comprising:

invalid bit polarity setting processing to be performed by an invalid bit polarity setting unit, when there exists an invalid bit having no data corresponding to data making up said input video signal in the specified transmission format of said output video signal, to set a polarity of said invalid bit existing in the specified transmission format of said output video signal having said invalid bit to be same as a polarity of one valid data bit before valid data bit in terms of time series.

14. A video signal processing method to be used in a video signal processing circuit for performing predetermined signal processing on an input video signal to transmit an output video signal in a form of a specified transmission format through a video signal line, wherein said video signal processing circuit is configured as a master-side device to which a slave-side device having a plurality of data storing devices and an address is connected through said video signal line and which outputs said address and a signal demanding transmitting/receiving operations, in every determined period, to said slave-side device and transmits said output video signal or receives data from said slave-side device and outputs device selection bit data for selection of each of said data storing devices of said slave-side device at time of transmitting mode and wherein an invalid bit polarity setting unit performs an invalid bit polarity setting process of counting a number of low and high levels received from said slave-side device in every predetermined period to compare a numerical size between said number of low levels and number of high levels for judgment and to set, based on a result of the judgment, a polarity of said device selection bit data which becomes invalid bit at time of receiving mode during which said each of storing devices of said slave-side devices is not selected.

15. The video signal processing method according to claim 14, wherein, in said invalid bit setting processing, a transmission mode judging process is performed by said transmission mode judging unit to judge whether said video signal processing circuit is in a transmitting mode or in a receiving mode based on the demand for transmitting/receiving in every predetermined period and a counting process is performed by said counting unit to count said number of low and high levels of said data received from said slave-side device when said video signal processing circuit is judged to be in said receiving mode and an invalid bit polarity determining process is performed by said invalid bit determining unit to compare a numerical size between said number of low levels and said number of high levels counted by said counting unit for judgment in every predetermined period to determine a polarity of said invalid bit based on a result of the judgment.

16. A video signal processing method to be used in a video signal processing circuit for performing predetermined signal processing on an input video signal to transmit an output video signal in a form of a specified transmission format through a video signal line, wherein said video signal processing circuit is configured as a master-side device to which a slave-side device having a plurality of data storing devices and an address is connected through said video signal line and which outputs said address and a signal demanding transmitting/receiving operations, in every determined period, to said slave-side device and transmits said output video signal or receives data from said slave-side device and outputs device selection bit data for selection of each of said data storing devices of said slave-side device at time of transmitting mode and wherein an invalid bit polarity setting unit performs an invalid bit polarity setting process of setting a polarity of said device selection bit data which becomes invalid data at time of receiving mode during which each of said data storing devices of said slave-side device to be same as a polarity of one valid data bit before valid data bit in terms of time series.