DECISION FEEDBACK EQUALIZER AND TRANSCEIVER

• US 20120201289A1
• Filed: 09/13/2011
• Published: 08/09/2012
• Est. Priority Date: 09/13/2010
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Semtech Canada Corp. (Semtech Corporation)
• Inventors: ABDALLA, Mohamed, REZAYEE, Afshin, CASSAN, David, VAN IERSSEL, Marcus, HOLDENRIED, Chris, SADR, Saman
• Granted Patent: US 8,879,618 B2
• Time in Patent Office: Days
• US Class Current: 375/233
• CPC Class Codes: H04L 2025/03624 Zero-forcing
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0276 Arrangements for coupling common mode signals
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence

Abstract

A decision feedback equalizer, transceiver, and method are provided, the equalizer having at least one comparator, the at least one comparator comprising a first stage, comprising a main branch having two track switches with a resistive load, an offset cancellation branch, a plurality of tap branches with transistor sizes smaller than the main branch, in which previous decisions of the equalizer are mixed with the tap weights using current-mode switching, and a cross coupled latch branch; and a second stage, comprising a comparator module for making decisions based on the outputs of the first stage and a clock input, and a plurality of flip-flops for storing the output of the comparator module.

Claims

1. A method for adapting an equalizer having a plurality of taps spaced sequentially at periods of one clock unit for observing a digital data system response produced by a digital system, comprising:

applying an arbitrary digital data sequence to the digital system;

detecting a first predetermined digital data pattern in the data sequence;

calculating a first error signal for a first tap of the plurality of taps based on the system response to the first data pattern;

using the first error signal to adapt the first tap; and

repeating the steps of detecting a data pattern, calculating an error signal, and adapting the tap for each tap other than the first tap in the plurality of taps,

wherein;

the digital data pattern used in conjunction with a given tap at position k in the sequence of taps has equal symbol values at positions (m−

k) and (m−

k−

1) and different symbol values at positions (m−

p) and (m−

p−

1), where p is not equal to k, for some value of m; and

the error signal calculated for the tap at sequential position k is proportional to the sum of the values of the pulse response of the system measured at the zero crossing directly before and after the lone bit of the pulse.

2. The method of claim 1, wherein the equalizer comprises a decision feedback equalizer.

3. The method of claim 1, wherein the plurality of taps comprises five taps.

4. The method of claim 1, wherein the taps are adapted sequentially in time according to their sequential positions.

5. The method of claim 1, the system further comprising a clock and data recovery stage having comparators used by the clock and data recovery stage to sample the data and obtain edge information for decision feedback adaptation, wherein the clock and data recovery stage comparators are also used to obtain edge information for adapting the taps of the equalizer.

6. The method of claim 1, wherein adapting a tap comprises applying de-emphasis or pre-emphasis based on the calculated error signal.

7. The method of claim 1, wherein the system comprises at least one far-end transmit pre-emphasis tap, the method further comprising:

transmitting at least one of the calculated error signals to the at least one far-end transmit pre-emphasis tap; and

adapting the at least one far-end transmit pre-emphasis tap based on the at least one transmitted calculated error signal.

8. The method of claim 1, wherein the plurality of taps comprises N taps, and wherein the equalizer further comprises a linear equalizer, further comprising:

detecting a data pattern in the data sequence having equal symbol values at positions (m−

k) and (m−

k−

1) for tap position k having values from 1 to N;

calculating a linear equalizer error signal which is proportional to the sum of the first N samples of the pulse response at each data edge following the symbol at position m; and

adapting the linear equalizer using the linear equalizer error signal.

9. The method of claim 1, wherein the linear equalizer comprises a continuous time linear equalizer.

10. A decision feedback equalizer having at least one comparator, the at least one comparator comprising:

a first stage, comprising;

a main branch having two track switches with a resistive load;

an offset cancellation branch;

a plurality of tap branches with transistor sizes smaller than the main branch, in which previous decisions of the equalizer are mixed with the tap weights using current-mode switching; and

a cross coupled latch branch; and

a second stage, comprising;

a comparator module for making decisions based on the outputs of the first stage and a clock input; and

a plurality of flip-flops for storing the output of the comparator module.

11. The decision feedback equalizer of claim 10, wherein the offset cancellation branch has the same structure as the main branch.

12. The decision feedback equalizer of claim 10, wherein the at least one comparator comprises two edge comparators and two center comparators.

13. The decision feedback equalizer of claim 10, wherein the at least one comparator is implemented using a pseudo-current-mode logic topology.

14. The decision feedback equalizer of claim 13, further comprising a continuous time linear equalizer which comprises:

a differential pair input stage;

an active inductive load;

a common mode feedback amplifier for setting the common mode for the at least one pseudo-current-mode logic decision feedback equalizer comparator.

15. The decision feedback equalizer of claim 10, further comprising a programmable attenuator having a plurality of branches, each branch comprising:

a series switch;

a shunt switch; and

a capacitor which can be changed from a series capacitor to a shunt capacitor based on the state of the series switch and the shunt switch.

16. The decision feedback equalizer of claim 10, wherein the at least one comparator is implemented as a differential pseudo-current mode logic structure comprising a cascade of a first NMOS transistor in common source orientation in series with a second NMOS transistor, wherein the second NMOS transistor acts as a switch and is connected at the drain terminal of the first transistor.

17. A receiver, comprising:

a digitally programmable termination unit;

a digitally programmable attenuator;

a continuous time linear equalizer;

an envelope detector;

an automatic gain control loop;

a half-rate decision feedback equalizer;

a plurality of flip flops for storing the output of the decision feedback equalizer;

a de-serializer; and

a clock and data recovery circuit comprising;

a bang-bang half-rate phase detector;

a loop filter having a proportional path and an integral path; and

a current digital to analog converter driving a ring voltage controlled oscillator.

18. A transmitter, comprising:

a clock multiplication unit;

a deserializer; and

a transmit driver comprising;

a plurality of line and pre-drivers, each line and pre-driver comprising;

a digital multiplexor;

a pre-driver cell;

a delay control block for controlling the delay of the pre-driver cell; and

an H-bridge driver cell;

a digital control block for controlling the delay control block;

a common-mode control block having a replica circuit and a buffer;

at least one digitally programmable on-chip termination resistor; and

a bias generator.