THROUGH SILICON VIAS USING CARBON NANOTUBES

• US 20120202347A1
• Filed: 02/06/2012
• Published: 08/09/2012
• Est. Priority Date: 02/07/2011
• Status: Abandoned Application

• Current Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Original Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Inventors: READY, WILLIAM JUDSON, Turano, Stephan
• Application Number:
  US13/366,545
• Publication Number:
  US 20120202347A1
• Time in Patent Office: Days
• US Class Current: 438/666
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/30655 comprising alternated and repeated etching and passivation steps, e.g. Bosch process
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/1094 Conducting structures comprising nanotubes or nanowires
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The various embodiments of the present invention provide carbon nanotube (CNT)-based TSVs and methods of making the same. The CNT-based TSVs embodiments comprise a silicon wafer having a plurality of through-vias defined therein, and a support layer comprising a CNT catalyst layer disposed beneath the silicon wafer to facilitate CNT growth through the plurality of through-vias. Once CNT arrays have grown inside and through the through-vias, the support layer and accompanying CNT catalyst layer can be removed from the silicon wafer, which will result in the CNTs remaining in the TSVs.

Claims

1. A method of making through silicon vias with carbon nanotube interconnects, the method comprising:

placing a silicon wafer mold comprising a plurality of holes onto a carbon nanotube growth source;

forming carbon nanotubes within at least a portion of the plurality of holes; and

separating the carbon nanotube growth source from the silicon wafer mold so that the carbon nanotubes formed within at least a portion of the plurality of holes remain substantially within the plurality of holes, thereby forming through silicon vias.

2. The method of claim 1, further comprising patterning a top surface of the silicon wafer.

3. The method of claim 1, wherein the carbon nanotube growth source comprises a metal.

4. The method of claim 3, wherein the metal is iron, nickel, or cobalt.

5. The method of claim 1, further comprising forming metal electrical contacts on at least a portion of the carbon nanotubes.

6. The method of claim 1, wherein the carbon nanotube growth source is separated from the silicon wafer mold via shearing.

7. The method of claim 1, wherein the plurality of holes in the silicon wafer have an average diameter of between about 10 and about 100 micrometers and an average depth of between about 150 and about 500 micrometers.

8. A method of making through silicon vias utilizing carbon nanotubes, comprising:

coating a bottom surface of a silicon wafer with a carbon nanotube catalyst layer followed by support layer;

etching a plurality of holes through the silicon wafer such that the plurality of holes extend from a top surface of the silicon wafer to the bottom side of the silicon wafer but do not penetrate the carbon nanotube catalyst layer or support layer; and

growing carbon nanotubes through at least a portion of the plurality of holes.

9. The method of claim 8, further comprising patterning the top surface of the silicon wafer.

10. The method of claim 8, wherein the carbon nanotube catalyst layer is a metal.

11. The method of claim 10, wherein the metal is iron, nickel, or cobalt.

12. The method of claim 8, wherein the carbon nanotube catalyst layer is about 0.5 to about 10 nanometers in thickness.

13. The method of claim 8, wherein the support layer is 5 micrometers or less in thickness.

14. The method of claim 8, wherein the silicon wafer is about 150 to about 500 micrometers in thickness.

15. The method of claim 8, wherein the silicon wafer mold is further selectively metalized with an additional metal to serve as an electrical contact layer.

16. The method of claim 8, further comprising forming metal electrical contacts on at least a portion of the carbon nanotubes.

17. The method of claim 8, wherein the carbon nanotube catalyst layer is also an electrical contact layer.

18. The method of claim 8, further comprising separating the silicon wafer mold from the carbon nanotube catalyst layer and support layer via shearing, chemical or plasma etching, or polishing.

19. The method of claim 8, wherein the support layer is an oxide layer.

20. The method of claim 8, wherein the support layer is made of a material having a higher melting temperature than the carbon nanotube deposition temperature.

21. The method of claim 8, wherein the carbon nanotubes are grown using a chemical vapor deposition process.