Memory System with Calibrated Data Communication

• US 20120204054A1
• Filed: 04/13/2012
• Published: 08/09/2012
• Est. Priority Date: 10/19/1999
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared LeVan, Donnelly, Kevin S., Sidiropoulos, Stefanos, Stark, Donald C., Horowitz, Mark A., Yu, Leung, Vu, Roxanne, Kim, Jun, Garlepp, Bruno W., Ho, Tsyr-Chyang, Lau, Benedict Chung-Kwong
• Granted Patent: US 8,630,317 B2
• Time in Patent Office: Days
• US Class Current: 713/400
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Claims

1. An integrated circuit device comprising:

a transmitter circuit operable to transmit a timing signal over a first wire to a dynamic random access memory (DRAM), where the DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value; and

a receiver circuit operable to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire,

where the transmitter circuit;

in a first mode, repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and

in a second mode, transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values, in connection with a write operation to the DRAM.

2. The integrated circuit device of claim 1, wherein the timing signal is a clock signal.

3. The integrated circuit device of claim 1, wherein the timing signal is a calibration-shifted internal transmit clock signal, the calibration-shifted internal transmit clock signal has a phase shift of 90 degrees relative to a normal output clock signal of the transmitter circuit.

4. The integrated circuit device of claim 1, wherein the plurality of wires comprise a data bus.

5. The integrated circuit device of claim 1, wherein the first mode corresponds to a calibration mode and the second mode corresponds to a normal operation mode of the integrated circuit device.

6. The integrated circuit device of claim 1, wherein, in the first mode, the transmitter circuit locks a current timing offset used to generate a respective offset version of the timing signal when the sampled values received from the DRAM changes from a logical zero to a logical one or vice versa, and wherein the timing offset is stored in a write offset register associated with the DRAM.

7. The integrated circuit device of claim 1, wherein the DRAM is a first DRAM of a plurality of DRAMs operable to communicate with the transmitter circuit, and wherein the transmitter circuit is operable to transmit a respective timing signal to and receive respective sampled values from each of the plurality of DRAMs and to operate in the first and second modes with respective to each of the plurality of DRAMs, respectively.

8. The integrated circuit device of claim 1, wherein the transmitter circuit enters the first mode periodically to recalibrate the write timing offset associated with the DRAM.

9. The integrated circuit device of claim 1, wherein the transmitter circuit enters the first mode to recalibrate the write timing offset associated with the DRAM upon detection of a predetermined threshold number of bit errors in the second mode.

10. The integrated circuit device of claim 1, further comprising:

a Delay-Locked-Loop (DLL) or Phase-Locked-Loop (PLL) circuit operable to produce a normal output clock signal and a calibration-shifted internal transmit clock signal.

11. The integrated circuit device of claim 1, wherein a data rate of the first signal corresponds to a period larger than a time memory of a data bus connecting the transmitter circuit and the receiver circuit.

12. The integrated circuit device of claim 11, wherein the time memory of the data bus corresponds to twice an electrical length of the data bus.