SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEVICES VIA A MAIN MEMORY SYSTEM

• US 20120204079A1
• Filed: 11/22/2011
• Published: 08/09/2012
• Est. Priority Date: 02/08/2011
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Diablo Technologies Incorporated (Rambus Inc.)
• Inventors: Takefman, Michael L., Amer, Maher, Badalone, Riccardo
• Granted Patent: US 8,713,379 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence
• CPC Class Codes: H03M 13/27 : using interleaving techniques
• CPC Class Codes: H04L 9/0662 : with particular pseudorandom sequence generator

Abstract

A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.

Claims

1. A system comprising:

a computer processing unit;

a memory module;

a memory bus that connects the computer processing unit and the memory module; and

a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.

2. The system of claim 1, wherein the system further comprises an ASIC that processes address and data bus signals received from and sent to the memory bus.

3. The system of claim 1 further comprising buffers that provide retiming of data bursts from the computer processing unit.

4. The system of claim 1 further comprising one or more ranks of DRAM modules.

5. The system of claim 2, further comprising a software driver that communicates commands to the ASIC.

6. The system of claim 2, wherein the system detects and initializes the ASIC after BIOS memory test operations are performed and prior to booting an operating system.

7. The system of claim 6, wherein initializing the ASIC includes learning the data scramble sequence the computer processing unit uses by solving for a generator vector associated with each address bus signal.

8. The system of claim 6, wherein initializing the ASIC includes loading a data scramble sequence from at least one of a serial ROM and an SMBus, wherein the data scramble sequence is used by the computer processing unit to solve for a generator vector associated with each address bus signal.

9. The system of claim 6, wherein initializing the ASIC includes generating a substantially linear address mapping that maps the address bus signals to a set of address signals internal to the ASIC.

10. The system of claim 6, wherein initializing the ASIC includes loading a substantially linear address mapping configuration from at least one of a serial ROM and an SMBus, wherein the substantially linear address mapping maps the address bus signals to a set of address signals internal to the ASIC.

11. The system of claim 6, wherein initializing the ASIC includes learning the ECC the computer processing unit uses by solving for a generator vector associated with each data bus signal.

12. The system of claim 6, wherein initializing the ASIC includes loading ECC configuration parameters from at least one of a serial ROM and an SMBus, wherein the ECC configuration parameters are used by the computer processing unit to solve for a generator vector associated with each data bus signal.

13. The system of claim 6, wherein initializing the ASIC includes putting the ASIC in a learning mode by writing multiple data patterns sequentially to the ASIC and comparing a sequence of the number of bit changes between each consecutive write with a mode unlock sequence.

14. The system of claim 2, wherein the ASIC processing address and data but signals includes unscrambling a data value received from the computer processing unit and scrambling a value for sending to the computer processing unit, the unscrambling and scrambling is performed based on associated address values.

15. The system of claim 2, wherein the ASIC processing address and data bus Signals includes generating an ECC value based on an associated data value.

16. The system of claim 2, wherein the ASIC includes a scrubber block that responds to memory reads to addresses that are not readable.

17. The system of claim 1, wherein the co-processing unit or input/output device includes an encryption unit.

18. The system of claim 1, wherein the co-processing unit or input/output device includes a compression unit.

19. The system of claim 1, wherein the co-processing unit or input/output device includes a digital signal processing unit.

20. The system of claim 1, wherein the co-processing unit or input/output device includes an image processing unit.

21. The system of claim 1, wherein the co-processing unit or input/output device includes a pattern matching unit.

22. The system of claim 1, wherein the co-processing unit or input/output device includes a wireless communications unit.

23. The system of claim 1, wherein the co-processing unit or input/output device includes a RAID control unit.

24. The system of claim 1, wherein the co-processing unit or input/output device includes a non-volatile memory storage device.

25. The system of claim 24, further comprising a memory controller, wherein the memory controller detects the non-volatile memory storage device as one of a RDIMM, a UDIMM, and a LRDIMM.

26. A method of learning scramble generator vectors that are utilized by a computer system to scramble data values based on a set of address signals, comprising the steps of:

instructing the computer system to write a zero data pattern to address zero to generate a first scrambled data value;

storing the first scrambled data value as one of the scramble generator vectors; and

for each one signal in the set of address signals,

setting only the one signal to “

1”

value while other signals in the set of address signals are set to “

0”

value,

writing a zero data pattern to an address corresponding to the address signals to generate a second scrambled data value,

performing a bitwise XOR operation of the first scrambled data value and the second scrambled data value to generate a scramble generator vector associated with the one of the address signals, and

storing the scramble generator vector associated with the one of the address signals.

27. A method of learning ECC generator vectors that are utilized by a computer system to generate ECC values based on a set of data signals, comprising the steps of:

instructing the computer system to write a zero data pattern to address zero to generate a first ECC value;

determine whether the first ECC value is inverted; and

for each one signal in the set of data signals,

setting only the one signal to “

1”

value while other signals in the set of data signals are set to “

0”

value,

writing a data pattern corresponding to the set of data signals to generate a second ECC value, and

storing the second ECC value as an ECC generator vector associated with the one signal.