MULTI-MODE PHOTODETECTOR

• US 20120205522A1
• Filed: 02/08/2012
• Published: 08/16/2012
• Est. Priority Date: 02/10/2011
• Status: Active Grant

• Current Assignee: Stmicroelectronics (Research & Development) Limited (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics (Research & Development) Limited (STMicroelectronics NV)
• Inventors: Richardson, Justin, Henderson, Robert
• Granted Patent: US 8,822,900 B2
• Time in Patent Office: Days
• US Class Current: 250/214.1
• CPC Class Codes: H04N 25/57 Control of the dynamic range
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/773 comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

A photodetector includes a photodiode and output circuitry coupled to the photodiode. The photodetector is configurable for operation in at least two modes. A first configurable mode operates the photodetector as an integrating sensor. In this first mode, a bias voltage across the photodiode is set below the breakdown voltage of the photodiode and the output circuitry is configured to read an analog integration output voltage from the photodiode. A second configurable mode operates the photodetector as a single photon avalanche detector. In this second mode, the bias voltage across the photodiode is set above the breakdown voltage of the photodiode and the output circuitry is configured to read an avalanche output voltage.

Claims

1. A photodetector, comprising:

a photodiode;

a bias terminal operable to receive an excess bias voltage and to set a bias voltage across the photodiode;

reset circuitry operable to control the bias voltage; and

output circuitry operable to read a voltage that depends on photons incident on the photodiode,

wherein the photodetector is operable in a first mode as an integrating sensor with the bias voltage being set below the breakdown voltage of the photodiode and with the output circuitry operable to read an analog integration output voltage from the photodiode; and

wherein the photodetector is operable in a second mode as a single photon avalanche detector with the bias voltage being set above the breakdown voltage of the photodiode and with the output circuitry operable to read an avalanche output voltage.

2. The photodetector according to claim 1, wherein the avalanche output voltage comprises a digital avalanche output voltage indicating an avalanche of the photodiode.

3. The photodetector according to claim 2, further comprising digital output circuitry operable, in the second mode, to buffer the digital avalanche output voltage.

4. The photodetector according to claim 1, wherein the avalanche output voltage comprises an analog avalanche output voltage responsive to timing of avalanches of the photodiode.

5. The photodetector according to claim 4, further comprising a current source and a capacitor and wherein, in the second mode, the analog avalanche output voltage is read from the capacitor.

6. The photodetector according to claim 4, wherein the analog avalanche output voltage is proportional to a time interval between a clock signal and an avalanche of the photodiode.

7. The photodetector according to claim 4, wherein the analog avalanche output voltage is proportional to a count of avalanches of the photodiode in a set time interval.

8. The photodetector according to claim 4, wherein the output circuitry comprises separate circuitry to read the integration output voltage from the photodiode in the first mode and to read the analog avalanche output voltage in the second mode.

9. The photodetector according to claim 4, wherein the output circuitry comprises shared circuitry both to read the integration output voltage from the photodiode in the first mode and to read the analog avalanche output voltage in the second mode.

10. The photodetector according to claim 1, wherein, in the first mode, the reset circuitry is operable as a switch to reset the bias voltage after an integration period.

11. The photodetector according to claim 1, wherein, in the second mode, the reset circuitry is operable as a switch to actively quench an avalanche by reducing the bias voltage to below the breakdown voltage.

12. The photodetector according to claim 11, wherein, in the second mode, the reset circuitry is further operable to arm the photodiode by resetting the bias voltage above the breakdown voltage.

13. The photodetector according to claim 1, wherein, in the second mode, the reset circuitry is operable as a load to passively quench an avalanche by reducing the bias voltage to below the breakdown voltage.

14. The photodetector according to claim 1, wherein the reset circuitry is a transistor.

15. The photodetector according to claim 1, wherein at least part of the output circuitry is coupled to the photodiode and operable in the first mode as a source follower to read the integration output voltage from the photodiode and operable in the second mode as a gate to produce the avalanche output voltage.

16. An imaging device, comprising:

a memory;

a processor; and

an image sensor coupled to at least one of the memory and processor,

wherein the image sensor comprises a plurality of photodetectors, each photodetector including a photodiode and output circuitry, and each photodetector being operable in at least two modes including;

a first mode as an integrating sensor with a bias voltage across the photodiode being set below the breakdown voltage of the photodiode and with the output circuitry operable to read an analog integration output voltage from the photodiode; and

a second mode as a single photon avalanche detector with the bias voltage across the photodiode being set above the breakdown voltage of the photodiode and with the output circuitry operable to read an avalanche output voltage.

17. The device of claim 16, wherein each photodetector further comprises reset circuitry operable to control the bias voltage across the photodiode.

18. The imaging device of claim 16, wherein the memory, the processor and the imaging sensor are supported by a housing of a camera.

19. A photodetector, comprising:

a photodiode and output circuitry, said photodetector being operable in at least two modes including;

a first mode as an integrating sensor wherein a bias voltage across the photodiode is set below the breakdown voltage of the photodiode and the output circuitry is configured to read an analog integration output voltage from the photodiode; and

a second mode as a single photon avalanche detector wherein the bias voltage across the photodiode is set above the breakdown voltage of the photodiode and the output circuitry is configured to read an avalanche output voltage.

20. The photodetector according to claim 19, wherein the output circuitry comprises separate circuitry to read the integration output voltage from the photodiode in the first mode and to read an analog avalanche output voltage in the second mode.

21. The photodetector according to claim 19, wherein the output circuitry comprises shared circuitry both to read the integration output voltage from the photodiode in the first mode and to read an analog avalanche output voltage in the second mode.

22. The photodetector according to claim 19, further comprising reset circuitry operable to control the bias voltage across the photodiode.

23. The photodetector according to claim 22, wherein, in the first mode, the reset circuitry is operable as a switch to reset the bias voltage after an integration period.

24. The photodetector according to claim 22, wherein, in the second mode, the reset circuitry is operable as a switch to actively quench an avalanche by reducing the bias voltage to below the breakdown voltage.

25. The photodetector according to claim 24, wherein, in the second mode, the reset circuitry is further operable to arm the photodiode by resetting the bias voltage above the breakdown voltage.

26. The photodetector according to claim 22, wherein, in the second mode, the reset circuitry is operable as a load to passively quench an avalanche by reducing the bias voltage to below the breakdown voltage.

27. A method, comprising:

controlling a photodetector to operate in at least two modes, wherein controlling comprises;

for a first mode, where the photodetector operates as an integrating sensor, setting a bias voltage across a photodiode below the breakdown voltage of the photodiode and configuring output circuitry coupled to the photodiode to read an analog integration output voltage from the photodiode; and

for a second mode, where the photodetector operates as a single photon avalanche detector, setting the bias voltage across the photodiode above the breakdown voltage of the photodiode and configuring the output circuitry to read an avalanche output voltage.