ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20120205647A1
• Filed: 12/06/2011
• Published: 08/16/2012
• Est. Priority Date: 02/11/2011
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Heo, Seong-Kweon
• Granted Patent: US 8,575,605 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

An organic light-emitting display device includes: a substrate having a transistor region and a thin-film transistor having a gate electrode, a source/drain electrode and an active layer sequentially formed on the transistor region, wherein a portion of the source/drain electrode is between the active layer and substrate.

Claims

1. An organic light-emitting display device comprising:

a substrate having a transistor region; and

a thin-film transistor having a gate electrode, a source/drain electrode and an active layer sequentially formed on the substrate at the transistor region,

wherein a portion of the source/drain electrode is between the active layer and the substrate.

2. The device of claim 1, wherein the source/drain electrode is separated from the gate electrode by a gate insulating film.

3. The device of claim 2, wherein portions of a back surface of the active layer are in contact with the source/drain electrode, and

wherein the other portion of the back surface of the active layer is in contact with the gate insulating film.

4. The device of claim 2, wherein the source/drain electrode is on the gate insulating film such that a recessed portion exposing a portion of the gate insulating film is at a location corresponding to a central portion of the gate electrode.

5. The device of claim 4, wherein the active layer is in contact with the source/drain electrode at an inner surface of the recessed portion.

6. The device of claim 4, wherein a width of the recessed portion is greater than or equal to a width of the gate electrode.

7. The device of claim 1, wherein the active layer comprises at least one of gallium-indium-zinc oxide (GIZO) or hafnium-indium-zinc oxide (HIZO).

8. An organic light-emitting display device comprising:

a substrate having a transistor region; and

a thin-film transistor having a gate electrode, a source/drain electrode and an active layer sequentially formed on the substrate at the transistor region,

wherein a portion of the source/drain electrode is between the active layer and the substrate, and a proportion of the gate electrode which is overlapped by the source/drain electrodes is about 30% or less of a width of the gate electrode.

9. The device of claim 8, wherein a parasitic capacitance between the gate electrode and the source/drain electrode is about 50 fF or less.

10. An organic light-emitting display device comprising:

a substrate having a pixel region, a transistor region, and a capacitor region;

pixel electrodes on the substrate;

gate electrodes on the pixel electrodes of the transistor region and the capacitor region, respectively;

a gate insulating film on the gate electrodes;

source/drain electrodes on the gate insulating film such that a recessed portion exposing a portion of the gate insulating film is located at a location corresponding to a central portion of the gate electrode of the transistor region;

an active layer in the recessed portion and having portions in contact with the source/drain electrodes of the transistor region and the other portion in contact with the gate insulating film at an inner surface of the recessed portion; and

a passivation film on the active layer.

11. The device of claim 10, wherein the pixel electrodes comprise indium tin oxide (ITO).

12. The device of claim 10, wherein the active layer comprises at least one of GIZO or HIZO.

13. The device of claim 10, wherein the passivation film comprises a multilayer film comprising at least one of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

14. The device of claim 13, wherein the silicon oxide film or the silicon oxynitride film is formed at an interface of the passivation film with the active layer, and the silicon nitride film is formed on the silicon oxide film or the silicon oxynitride film.

15. A method of manufacturing an organic light-emitting display device, the method comprising:

forming gate electrodes and pixel electrodes on a substrate having a pixel region, a transistor region, and a capacitor region;

forming a gate insulating film on the gate electrodes;

forming source/drain electrodes on the gate insulating film;

forming an active layer on the source/drain electrode of the transistor region; and

forming a passivation film and a pixel defining layer, and then etching the passivation film and the pixel defining layer of the pixel region to expose the pixel electrode of the pixel region,

wherein a portion of the source/drain electrode of the transistor region is between the active layer and the substrate.

16. The method of claim 15, wherein the exposing of the pixel electrode of the pixel region comprises:

forming an aperture region by patterning the pixel defining layer of the pixel region; and

dry-etching the passivation film disposed under and exposed through the aperture region of the pixel defining layer before a curing process of the pixel defining layer.

17. A method of manufacturing an organic light-emitting display device, the method comprising:

forming gate electrodes and pixel electrodes on a substrate having a pixel region, a transistor region, and a capacitor region;

forming a gate insulating film on the gate electrodes;

forming source/drain electrodes on the gate insulating film;

forming an active layer on the source/drain electrode of the transistor region;

forming a passivation film and then etching the passivation film of the pixel region to expose the pixel electrode of the pixel region; and

forming a pixel defining layer on the passivation film and then etching the pixel defining layer of the pixel region to expose the pixel electrode of the pixel region,

wherein a portion of the source/drain electrodes of the transistor region is between the active layer and the substrate.

18. The method of claim 17, wherein in the forming of the active layer, portions of a back surface of the active layer are in contact with the source/drain electrodes, and the other portion of the back surface of the active layer is made to contact the gate insulating film.

19. The method of claim 17, wherein the forming of the source/drain electrodes on the gate insulating film further comprises forming a recessed portion, which exposes a portion of the gate insulating film, at a location corresponding to a central portion of the gate electrode of the transistor region.

20. The method of claim 19, wherein in the forming of the active layer, the active layer is made to contact the source/drain electrodes of the transistor region at an inner surface of the recessed portion.

21. The method of claim 20, wherein a width of the recessed portion is greater than or equal to a width of the gate electrode of the transistor region.

22. The method of claim 17, wherein the active layer comprises at least one of GIZO or HIZO.