Thin-Film Electronic Devices Including Pre-Deformed Compliant Substrate

• US 20120205656A1
• Filed: 04/23/2012
• Published: 08/16/2012
• Est. Priority Date: 05/20/2008
• Status: Abandoned Application

• Current Assignee: Palo Alto Research Center, Inc. (Xerox Holdings Corp.)
• Original Assignee: Palo Alto Research Center, Inc. (Xerox Holdings Corp.)
• Inventors: Lujan, Rene, Wong, William S., Greer, Julia R.
• Application Number:
  US13/453,881
• Publication Number:
  US 20120205656A1
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate

Abstract

A thin-film layered electronic device, or array of devices, is formed over a layer structure comprising a flexible substrate, a buffer layer, and a metal layer. The layer structure is annealed to permanently deform the layer structure beyond its plastic deformation limit. The thin-film electronic device is formed thereover by a process according to which all steps are performed at a temperature below that at which further plastic deformation of the buffer layer occurs. In-process strain and runout are reduced, improving device yield on flexible substrates. The metal layer forms a first layer of the thin-film layered device, or array of devices.

Claims

1. An electronic structure comprising:

a layer structure comprising;

a flexible substrate;

a buffer layer formed over said flexible substrate;

a metal layer formed over said buffer layer;

said layer structure permanently plastically deformed, said deformation the result of an annealing during which said layer structure in its entirety is heated to an anneal temperature beyond the plastic deformation limit of said layer structure, then cooled; and

a layered electronic device, formed over said layer structure such that the said metal layer forms a first layer of said layered electronic device.

2. The electronic structure of claim 1, wherein said buffer layer comprises a stacked structure of silicon dioxide and silicon nitride.

3. The electronic structure of claim 2, wherein said buffer layer comprises:

a silicon nitride layer in the range of 200-400 nanometers thick formed over said substrate; and

a silicon dioxide layer in the range of 200-400 nanometers thick formed over said silicon nitride layer.

4. The electronic structure of claim 3, wherein said silicon dioxide and said silicon nitride layers are substantially the same thickness.

5. The electronic structure of claim 4, wherein said silicon dioxide and said silicon nitride layers are each approximately 300 nanometers thick.

6. The electronic structure of claim 1, wherein said flexible substrate is polyethylene naphthalate.

7. The electronic structure of claim 1, wherein said metal layer is formed of tantalum, and is in the range of approximately 100-150 nanometers thick.

8. The electronic structure of claim 7, wherein said metal layer is approximately 120 nanometers thick.

9. The electronic structure of claim 1, wherein said layered electronic device is a transistor.

10. The electronic structure of claim 9, wherein said transistor has an active layer formed of amorphous silicon.

11. The electronic structure of claim 10, wherein said metal layer is formed of tantalum, and is in the range of approximately 100-150 nanometers thick and a portion thereof forms a gate of said transistor.

12. A thin-film transistor structure, comprising:

a layer structure comprising;

a flexible substrate;

a buffer layer formed over said flexible substrate;

a metal layer formed over said buffer layer;

said layer structure permanently plastically deformed by an annealing during which said layer structure is heated to an anneal temperature beyond the plastic deformation limit of said layer structure, then cooled; and

a transistor formed over and in physical contact with said layer structure such that a portion of said metal layer forms a gate structure of said transistor.

13. The thin-film transistor structure of claim 12, wherein said transistor comprises an amorphous silicon active layer.

14. The thin-film transistor structure of claim 12, wherein said buffer layer comprises:

a silicon nitride layer in the range of 200-400 nanometers thick formed over said substrate; and

a silicon dioxide layer in the range of 200-400 nanometers thick formed over said silicon nitride layer.

15. The thin-film transistor structure of claim 14, wherein said silicon dioxide and said silicon nitride layers are each approximately 300 nanometers thick.

16. A thin-film transistor structure, comprising:

a layer structure comprising;

a flexible substrate;

a buffer layer formed over said flexible substrate;

a metal layer formed over said buffer layer;

said layer structure permanently plastically deformed by an annealing during which said layer structure is heated to an anneal temperature beyond the plastic deformation limit of said layer structure, then cooled; and

an array comprising a plurality of electronic devices formed over and in physical contact with said layer structure, at least one of said electronic devices comprising a transistor, such that a portion of said metal layer forms a portion of each of said electronic devices.

17. The thin-film transistor structure of claim 16, wherein said transistor comprises an amorphous silicon active layer.

18. The thin-film transistor structure of claim 16, wherein said buffer layer comprises:

a silicon nitride layer in the range of 200-400 nanometers thick formed over said substrate; and

a silicon dioxide layer in the range of 200-400 nanometers thick formed over said silicon nitride layer.

19. The thin-film transistor structure of claim 18, wherein said silicon dioxide and said silicon nitride layers are each approximately 300 nanometers thick.

20. The thin-film transistor structure of claim 16, wherein said metal layer is formed of tantalum, and is in the range of approximately 100-150 nanometers thick.