SEMICONDUCTOR STRUCTURE HAVING VARACTOR WITH PARALLEL DC PATH ADJACENT THERETO

• US 20120205781A1
• Filed: 04/19/2012
• Published: 08/16/2012
• Est. Priority Date: 09/14/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Incorporated (International Business Machines Corporation)
• Inventors: Fried, David M., Nowak, Edward J.
• Granted Patent: US 8,598,683 B2
• Time in Patent Office: Days
• US Class Current: 257/595
• CPC Class Codes: H01L 29/93 Variable capacitance diodes, e.g. varactors

Abstract

A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and

a first terminal including;

a first deep trench located in the first region,

a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench;

a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric, and

a first electrical contact electrically coupling the first conductive inner electrode to the first region.

2. The semiconductor structure of claim 1, further comprising:

a second terminal further including;

a second deep trench located in the second region,

a second node dielectric abutting all but an upper portion of sidewalls and a bottom of the second deep trench;

a second conductive inner electrode inside the second node dielectric and electrically insulated from the second region by the second node dielectric, and

wherein the second electrical contact electrically couples the second conductive inner electrode to the second region.

3. The semiconductor structure of claim 1, wherein the semiconductor substrate includes a third region having the first polarity, the second region separating the first region and the third region, and further comprising:

a second terminal including;

a second deep trench located in the third region,

a second node dielectric abutting all but an upper portion of sidewalls and a bottom of the second deep trench;

a second conductive inner electrode inside the second node dielectric and electrically insulated from the third region by the second node dielectric, and

a second electrical contact electrically coupling the second conductive inner electrode to the third region.

4. The semiconductor structure of claim 2, wherein the first and third regions includes a n-type dopant and the second region includes a p-type dopant.

5. The semiconductor structure of claim 1, wherein the semiconductor substrate includes a third region having the second polarity, the second region separating the first region and the third region, and further comprising:

a second terminal including;

a second deep trench located in the third region,

a second node dielectric abutting all but an upper portion of sidewalls and a bottom of the second deep trench;

a second conductive inner electrode inside the second node dielectric and electrically insulated from the third region by the second node dielectric, and

a second electrical contact electrically coupling the second conductive inner electrode to the third region.

6. The semiconductor structure of claim 5, wherein the first region includes a n-type dopant, the second region includes a p-type dopant having a first concentration, and the third region includes a p-type dopant having a second concentration different than the first concentration.

7. A semiconductor structure comprising:

a semiconductor substrate having a first region of a first polarity, a second region of a second polarity adjacent to the first region and a third region having the first polarity, the second region separating the first region and the third region; and

a first terminal including;

a first deep trench located in the first region,

a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench;

a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric, and

a first electrical contact electrically coupling the first conductive inner electrode to the first region;

a connection region at a surface of the semiconductor substrate electrically coupling the first electrical contact to the first region; and

a second terminal including;

a second deep trench located in the third region,

a second node dielectric abutting all but an upper portion of sidewalls and a bottom of the second deep trench;

a second conductive inner electrode inside the second node dielectric and electrically insulated from the third region by the second node dielectric, and

a second electrical contact electrically coupling the second conductive inner electrode to the third region,

wherein the first and third regions includes a n-type dopant and the second region includes a p-type dopant.

8. The semiconductor structure of claim 7, wherein the first and third polarity are different from the second polarity based on a different dopant concentration or a doping of a different conductivity type.

9. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a semiconductor structure comprising;

a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and

a first terminal including;

a first deep trench located in the first region,

a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench;

a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric, and

a first electrical contact electrically coupling the first conductive inner electrode to the first region.

10. The design structure of claim 9, wherein the design structure comprises a netlist.

11. The design structure of claim 9, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

12. The design structure of claim 9, wherein the design structure includes at least one of test data, characterization data, verification data, or design specifications.