TESTING OF SEMICONDUCTOR CHIPS WITH MICROBUMPS

• US 20120206160A1
• Filed: 02/11/2011
• Published: 08/16/2012
• Est. Priority Date: 02/11/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: WU, Wei-Cheng, HU, Hsien-Pin, HOU, Shang-Yun, JENG, Shin-Puu, YU, Chen-Hua, YANG, Chao-Hsiang
• Granted Patent: US 8,797,057 B2
• Time in Patent Office: Days
• US Class Current: 324/756.07
• CPC Class Codes: G01R 1/0416 Connectors, terminals G01R1/0425 and G01R1/0433 take precedence; with measurement function for battery poles G01R31/364
• CPC Class Codes: G01R 31/2601 Apparatus or methods therefor G01R31/2607, G01R31/2642 take precedence
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/2893 Handling, conveying or loading, e.g. belts, boats, vacuum fingers G01R31/2867 takes precedence; handling semiconductor devices or wafers during manufacture or treatment H01L21/67
• CPC Class Codes: G01R 31/2896 Testing of IC packages; Test features related to IC packages containers per se H01L23/02, encapsulations per se H01L23/28
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0392 specifically adapted to include a probing step
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/0614 Circular array, i.e. array with radial symmetry
• CPC Class Codes: H01L 2224/0616 Random array, i.e. array with no symmetry
• CPC Class Codes: H01L 2224/1146 Plating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11849 : Reflowing
• CPC Class Codes: H01L 2224/13005 : Structure
• CPC Class Codes: H01L 2224/13083 : Three-layer arrangements
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 : Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/14131 : being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/16238 : the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/20752 : larger or equal to 20 microns less than 30 microns

Abstract

Test structures for performing electrical tests of devices under one or more microbumps are provided. Each test structure includes at least one microbump pad and a test pad. The microbump pad is a part of a metal pad connected to an interconnect for a device. A width of the microbump pad is equal to or less than about 50 μm. The test pad is connected to the at least one microbump pad. The test pad has a size large enough to allow circuit probing of the device. The test pad is another part of the metal pad. A width of the test pad is greater than the at least one microbump pad.

Claims

1. A test structure for performing electrical tests of devices under one or more microbumps, comprising:

at least one device; and

a metal pad connected to an interconnect for the at least one device, the metal pad comprising;

a first portion forming at least one microbump pad, wherein a width of the at least one microbump pad is equal to or less than about 50 μ

m, and

a second portion forming a test pad connected to the at least one microbump pad, wherein the test pad has a size large enough to allow circuit probing of the at least first device, and wherein a width of the test pad is greater than the at least one microbump pad.

2. The test structure of claim 1, wherein the least one microbump pad is for depositing a microbump in each of the at least one microbump pad, and wherein the microbump has a width in a range from about 20 μ

m to about 50 μ

m.

3. The test structure of claim 2, wherein a space between the at least one microbump pad and the test pad is between about 20 μ

m to about 80 μ

m.

4. The test structure of claim 1, wherein the test pad has a width greater than about 60 μ

m to allow circuit probe.

5. The test structure of claim 1, the metal pad is at a level of at least one of a top metal, a pad metal above the top metal, a redistribution layer, or a post passivation interconnect.

6. The test structure of claim 1, wherein the test pad is adapted to be covered after circuit probing by a passivation material to prevent particle and corrosion issues.

7. The test structure of claim 6, wherein the passivation material is at least one of a polyimide, a silicon oxide, or a silicon nitride.

8. The test structure of claim 1, wherein the at least one microbump pad includes 2 to 8 microbump pads, and wherein the 2 to 8 microbump pads are connected to the test pad, and wherein the 2 to 8 microbump pads are symmetrically distributed around the test pad to balance a stress induced by a formation of microbumps on the 2 to 8 microbump pads and to reduce interface delamination of microbumps formed on the 2 to 8 microbump pads.

9. The test structure of claim 1, wherein the at least one microbump pad includes 2 to 8 microbump pads, and wherein the 2 to 8 microbump pads are connected to the test pad, and wherein the 2 to 8 microbump pads are asymmetrically distributed around the test pad.

10. The test structure of claim 1, further comprising additional test pads, and wherein each test pad is connected to one or more microbumps for testing devices connected to the one or more microbumps, and wherein the test pad and the additional test pads are used to test inputs/outputs (I/Os) with different currents.

11. The test structure of claim 1, wherein the at least one microbump pad is covered by an under bump metallurgy (UBM) layer.

12. The test structure of claim 1, wherein outlines of the test pad and the at least one microbump pad are defined by a passivation layer.

13. The test structure of claim 1, wherein more than one device is connected to the at least one microbump pad.

14. A test structure for performing electrical tests of devices under one or more microbumps, comprising:

at least one microbump pad, wherein the at least one microbump pad is a part of a metal pad connected to an interconnect for at least a first device, and wherein a width of the at least one microbump pad is equal to or less than about 50 μ

m; and

a test pad connected to the at least one microbump pad, wherein the test pad has a size large enough to allow circuit probe involving at least the first device, and wherein the test pad is another part of the metal pad, and wherein a width of the test pad is greater than the at least one microbump pad;

wherein the test pad is covered after circuit probe by a passivation material to prevent particle and corrosion issues.

15. A method of forming and testing a test structure for electrical tests of devices under one or more microbumps, comprising:

depositing a first passivation layer over a metal pad on a semiconductor substrate;

defining at least one microbump pad connected to a test pad by patterning the first passivation layer, wherein the at least one microbump pad is connected to interconnect of a first device;

performing circuit probing on the test pad to electrically test devices connected to the at least one microbump pad;

forming a second passivation layer to cover the test pad and to expose the at least one microbump pad; and

forming a microbump on each of the at least one microbump pad.

16. The method of claim 15, wherein the at least one microbump pad is a part of the metal pad connected to interconnect for at least a first device, and wherein a width of the at least one microbump pad is equal to or less than about 50 μ

m, wherein the test pad connected to the at least one microbump pad, wherein in the test pad has a size large enough to allow circuit probe involving the at least first device, and wherein the test pad is another part of the metal pad, and wherein a width of the test pad is greater than the at least one microbump pad.

17. The method of claim 15, wherein an under bump metallurgy (UBM) layer is formed between the microbump and each of the at least one microbump pad underneath the microbump.

18. The method of claim 15, wherein the second passivation layer is deposited over the test pad to protect damaged surface due to circuit probe from causing particles and corrosion, and wherein the second passivation layer is at least one of a polyimide, an silicon oxide, or a silicon nitride layer.

19. The method of claim 15, wherein the microbump has a width in a range from about 20 μ

m to about 50 μ

m, and wherein a space between the at least microbump and the test pad is between about 20 μ

m to about 80 μ

m, and wherein the test pad has a width greater than about 60 μ

m to allow circuit probing.

20. The method of claim 15, wherein the at least one microbump pad includes 2 to 8 microbump pads, and wherein the 2 to 8 microbump pads are connected to the test pad, and wherein the 2 to 8 microbump pads are symmetrically distributed around the test pad to balance a stress induced by a formation of microbumps on the 2 to 8 microbump pads and to reduce interface delamination of microbumps formed on the 2 to 8 microbump pads.