SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20120208375A1
• Filed: 04/23/2012
• Published: 08/16/2012
• Est. Priority Date: 12/02/2002
• Status: Abandoned Application

• Current Assignee: Foundation for Advancement of International Science
• Original Assignee: Foundation for Advancement of International Science
• Inventors: Ohmi, Tadahiro, Sugawa, Shigetoshi, Teramoto, Akinobu, Akahori, Hiroshi, Nii, Keiichi
• Application Number:
  US13/453,206
• Publication Number:
  US 20120208375A1
• Time in Patent Office: Days
• US Class Current: 438/785
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02142 the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02301 in-situ cleaning
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/31654 of semiconductor materials, e.g. the body itself
• CPC Class Codes: H01L 21/318 composed of nitrides
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H₂O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of:

preparing a silicon semiconductor surface which has a predetermined crystal plane orientation;

isotropically oxidizing the silicon surface to form a self-sacrifice oxide film on the silicon surface to flatten the silicon surface into the prescribed arithmetical mean deviation of surface Ra;

removing the self-sacrifice oxide film to expose the flattened silicon surface;

cleaning the flattened silicon surface into a cleaned surface; and

forming a gate insulation film on the cleaned surface;

wherein;

the isotropically oxidizing step comprises the step of;

carrying out radical oxidation of the silicon surface within a radical oxidation atmosphere to form the self-sacrifice oxide film, and

wherein;

the step of forming the gate insulation film is performed within an oxygen radical atmosphere by using gas plasma generated in a mixed gas of a rare gas selected from at least one of argon, krypton and xenon and an oxygen gas by microwave excitation.

2. A method as claimed in claim 1, wherein the silicon surface is either a (100) crystal plane orientation or a (110) crystal plane orientation.

3. A method as claimed in claim 1, wherein the silicon surface is flattened to surface roughness (Ra) of 0.08 nm or less after the self-sacrifice oxide film is formed within the radical oxidation atmosphere.

4. A method as claimed in claim 1, wherein the self-sacrifice film is removed by the use of a mixed solution of HF and HCl mixed at the volume ratio of 1:

19.

5. A method as claimed in claim 1, wherein the gate insulation film includes at least one material selected from a group consisting of metal silicate, metal oxide, and metal nitride.

6. A method as claimed in claim 5, wherein the metal oxide consists of at least one selected from a group consisting of oxides of Si, Hf, Zr, Ta, Ti, Y, Nb, Na, Co, Al, Zn, Pb, Mg, Bi, La, Ce, Pr, Sm, Eu, Gd, Dy, Er, Sr, and Ba.