THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

• US 20120211745A1
• Filed: 03/02/2012
• Published: 08/23/2012
• Est. Priority Date: 09/04/2009
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ueda, Tomomasa, Nakano, Shintaro, Saito, Nobuyoshi, Hara, Yujiro, Uchikoga, Shuichi
• Granted Patent: US 9,209,311 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

According to one embodiment, a thin film transistor includes a gate electrode, a semiconductor layer, a gate insulating film, and a source electrode and a drain electrode. The semiconductor layer includes an oxide including at least one of gallium and zinc, and indium. The gate insulating film is provided between the gate electrode and the semiconductor layer. The source electrode and a drain electrode are electrically connected to the semiconductor layer and spaced from each other. The semiconductor layer includes a plurality of fine crystallites dispersed three-dimensionally in the semiconductor layer and has periodicity in arrangement of atoms.

Claims

1. A thin film transistor comprising:

a gate electrode;

a semiconductor layer including an oxide including at least one of gallium and zinc, and indium;

a gate insulating film provided between the gate electrode and the semiconductor layer; and

a source electrode and a drain electrode electrically connected to the semiconductor layer and spaced from each other,

the semiconductor layer including a plurality of fine crystallites dispersed three-dimensionally in the semiconductor layer and having periodicity in arrangement of atoms.

2. The transistor according to claim 1, wherein an average particle diameter of the fine crystallites having a particle diameter of 2 nanometers or more among the fine crystallites is 3.5 nanometers or less.

3. The transistor according to claim 2, wherein no lattice image is observed in a transmission electron microscope image of the semiconductor layer, and a bright spot based on the periodicity is observed in a Fourier transformed image of the transmission electron microscope image.

4. The transistor according to claim 3, further comprising a channel protection layer,

the gate electrode being provided on a major surface of a substrate,

the semiconductor layer is provided on an opposite side of the gate electrode from the substrate, and

the channel protection layer being provided on an opposite side of the semiconductor layer from the gate electrode.

5. The transistor according to claim 4, wherein the substrate is light transmissive.

6. The transistor according to claim 5, wherein the substrate is a glass substrate or a plastic substrate.

7. The transistor according to claim 4, wherein the channel protection layer is a silicon oxide film.

8. The transistor according to claim 3, wherein the semiconductor layer is provided on a major surface of a substrate, and the gate electrode is provided on an opposite side of the semiconductor layer from the substrate.

9. The transistor according to claim 8, wherein the substrate is light transmissive.

10. The transistor according to claim 9, wherein the substrate is a glass substrate or a plastic substrate.

11. The transistor according to claim 1, wherein a thickness of the semiconductor layer is 10 nanometers or more and 30 nanometers or less.

12. The transistor according to claim 1, further comprising a green color filter layer provided on the thin film transistor.

13. A method for manufacturing a thin film transistor including:

a gate electrode;

a semiconductor layer including an oxide including at least one of gallium and zinc, and indium, and including a plurality of fine crystallites dispersed three-dimensionally and having periodicity in arrangement of atoms;

a gate insulating film provided between the gate electrode and the semiconductor layer; and

a source electrode and a drain electrode electrically connected to the semiconductor layer and spaced from each other,

the method comprising;

forming a stacked film of the gate electrode, the gate insulating film, and an oxide film including at least one of gallium and zinc, and indium;

forming the fine crystallites in the oxide film by heat treatment of the stacked film at 320°

C. or more and 380°

C. or less; and

forming the source electrode and the drain electrode so as to be connected to the oxide film,

the forming the stacked film including

forming the oxide film on a major surface of a substrate, forming the gate insulating film made of a silicon oxide film on the oxide film, and forming the gate electrode on the gate insulating film so that the oxide film is covered with the gate insulating film, and

the forming the fine crystallites being performed in a state in which the oxide film is covered with the silicon oxide film constituting the gate insulating film.

14. The method according to claim 13, wherein

the forming the fine crystallites is performed before formation of a film constituting the source electrode and the drain electrode.

15. The method according to claim 13, wherein

the forming the stacked film includes forming a portion formed in an early phase of the forming the gate insulating film by a PE-CVD method using a gas flow ratio of SiH₄/N₂O of 1/100 or less.

16. A method for manufacturing a thin film transistor including:

a gate electrode;

a semiconductor layer including an oxide including at least one of gallium and zinc, and indium, and including a plurality of fine crystallites dispersed three-dimensionally and having periodicity in arrangement of atoms;

a gate insulating film provided between the gate electrode and the semiconductor layer; and

a source electrode and a drain electrode electrically connected to the semiconductor layer and spaced from each other,

the method comprising;

forming a stacked film of the gate electrode, the gate insulating film, and an oxide film including at least one of gallium and zinc, and indium;

forming the fine crystallites in the oxide film by heat treatment of the stacked film at 320°

C. or more and 380°

C. or less; and

forming the source electrode and the drain electrode so as to be connected to the oxide film,

the forming the stacked film including

forming the gate electrode on a major surface of a substrate, forming the gate insulating film on the gate electrode, forming the oxide film on the gate insulating film, and forming a channel protection layer made of a silicon oxide film on the oxide film so that the oxide film is covered with the channel protection layer, and

the forming fine crystallites being performed in a state in which the oxide film is covered with the silicon oxide film constituting the channel protection layer.

17. The method according to claim 16, wherein

the forming the fine crystallites is performed before formation of a film constituting the source electrode and the drain electrode.

18. The method according to claim 16, wherein

a formation temperature of the channel protection layer is 230°

C. or more.

19. The method according to claim 16, wherein

the formation of the channel protection layer is performed by a PE-CVD using TEOS.

20. The method according to claim 16, wherein the formation of the stacked film includes forming a portion formed in an early phase of the forming the cahnnel protection layer by a PE-CVD method using a gas flow ratio of SiH₄/N₂O of 1/100 or less.