Display Apparatus and Method of Manufacturing the Same

• US 20120211751A1
• Filed: 09/19/2011
• Published: 08/23/2012
• Est. Priority Date: 02/17/2011
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kim, Swae-Hyun, Yoon, YeoGeon, Park, Jae Hwa, Tae, Changil
• Granted Patent: US 8,614,443 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Abstract

A display apparatus includes a substrate and a plurality of pixels disposed on the substrate. Each pixel includes a gate electrode disposed on the substrate, a gate dielectric layer disposed on the substrate and the gate electrode, an oxide semiconductor pattern disposed on the gate dielectric layer, a first insulating pattern disposed on the oxide semiconductor pattern that overlaps the gate electrode, a second insulating pattern disposed on the oxide semiconductor pattern and spaced apart from the first insulating pattern, source and drain electrodes spaced apart from each other on the oxide semiconductor pattern, a pixel electrode pattern disposed on the second insulating pattern to make contact with the source electrode, and a channel area defined where the oxide semiconductor pattern overlaps the gate electrode. A high carrier mobility channel is formed in the channel area when a turn-on voltage is applied to the gate electrode.

Claims

1. A display apparatus comprising:

a substrate; and

a plurality of pixels disposed on the substrate, each pixel comprising;

a gate electrode disposed on the substrate;

a gate dielectric layer disposed on the substrate and the gate electrode;

an oxide semiconductor pattern that overlaps the gate electrode disposed on the gate dielectric layer;

a first insulating pattern disposed on the oxide semiconductor pattern that overlaps the gate electrode;

a second insulating pattern disposed on the oxide semiconductor pattern and spaced apart from the first insulating pattern;

a drain electrode disposed on the oxide semiconductor pattern;

a source electrode disposed on the oxide semiconductor pattern and spaced apart from the drain electrode; and

a pixel electrode pattern disposed on the second insulating pattern that contacts the drain electrode.

2. The display apparatus of claim 1, wherein the drain electrode covers a portion of the pixel electrode pattern.

3. The display apparatus of claim 1, wherein a sidewall of the second insulating pattern is aligned and coplanar with a sidewall of the pixel electrode pattern.

4. The display apparatus of claim 1, wherein the second insulating pattern is spaced apart from the gate electrode.

5. The display apparatus of claim 1, further comprising:

a plurality of gate lines that extend in a first direction;

a plurality of data lines that extend in a second direction crossing the first direction and disposed on the oxide semiconductor pattern, wherein the gate electrode protrudes from the gate line and the source electrode protrudes from the data line.

6. The display apparatus of claim 1, further comprising a common electrode disposed over the pixel electrode pattern for forming an electric field with the pixel electrode pattern, wherein the common electrode comprises a body portion and a plurality of branch portions branched from the body portion.

7. The display apparatus of claim 1, wherein the drain electrode covers the oxide semiconductor pattern between the first and second insulating patterns.

8. A method of manufacturing a display apparatus, comprising:

forming a gate electrode on a substrate;

sequentially forming a dielectric layer, an oxide semiconductor layer, an insulating layer, and a pixel electrode layer on the substrate;

patterning the pixel electrode layer and the insulating layer to form a first insulating pattern that overlaps the gate electrode, a second insulating pattern spaced apart from the first insulating pattern, and a pixel electrode pattern disposed on the second insulating pattern;

forming a source electrode and a drain electrode on the oxide semiconductor layer, the source electrode being spaced apart from the drain electrode; and

forming a common electrode on the pixel electrode pattern.

9. The method of claim 8, wherein patterning the pixel electrode layer and the insulating layer comprises forming a dummy electrode pattern on the first insulating pattern.

10. The method of claim 9, further comprising forming a first mask pattern on the pixel electrode layer to overlap the gate electrode and a second mask pattern thicker than the first mask pattern on the pixel electrode layer to overlap the gate electrode, wherein the pixel electrode layer and the insulating layer are patterned using the first and second mask patterns as an etching mask.

11. The method of claim 10, further comprising:

removing a portion of the second mask pattern to form a third mask pattern thinner than the second mask pattern;

removing the first mask pattern; and

removing the dummy electrode pattern using the third mask pattern as an etching mask.

12. The method of claim 11, wherein the third mask pattern is formed by a same process that removes the first mask pattern.

13. The method of claim 9, wherein patterning the pixel electrode layer and the insulating layer comprises exposing first and second portions of the oxide semiconductor layer respectively corresponding to areas on either side of the gate electrode.

14. The method of claim 13, wherein forming the source electrode and the drain electrode comprises:

forming a conductive layer on the oxide semiconductor layer;

forming a fourth mask pattern on the conductive layer to cover the first and second portions of the oxide semiconductor layer; and

removing the conductive layer and the oxide semiconductor layer using at least one of the fourth mask pattern, the source electrode, or the drain electrode using an etching mask.

15. The method of claim 9, further comprising:

forming, by a same process that forms the gate electrode, a common voltage line to transmit a common voltage and a gate line extended in a first direction;

forming, by a same process that forms the source and drain electrodes, a data line extended in a second direction crossing the first electrode, and

wherein common voltage line and the gate line are covered by the gate dielectric layer.

16. The method of claim 15, further comprising:

forming an interlayer dielectric layer on the source electrode, the drain electrode, and the pixel electrode pattern prior to forming the common electrode, wherein the interlayer dielectric layer covers the common voltage line, the gate line, and the data line.

17. The method of claim 16, further comprising:

forming, in a same process, a common contact hole, a gate contact hole, and a data contact hole through the interlayer dielectric layer and the gate dielectric layer to respectively expose the common voltage line, an end of the gate line, and an end of the data line, wherein the common electrode contacts the common voltage line through the common contact hole.

18. A display apparatus comprising:

a substrate; and

a plurality of pixels disposed on the substrate, each pixel comprising;

a gate electrode disposed on the substrate;

a gate dielectric layer disposed on the substrate and the gate electrode;

an oxide semiconductor pattern that overlaps the gate electrode disposed on the gate dielectric layer;

a first insulating pattern disposed on the oxide semiconductor pattern that overlaps the gate electrode;

a second insulating pattern disposed on the oxide semiconductor pattern and spaced apart from the first insulating pattern;

a drain electrode disposed on the oxide semiconductor pattern;

a source electrode disposed on the oxide semiconductor pattern and spaced apart from the drain electrode;

a pixel electrode pattern disposed on the second insulating pattern that contacts the drain electrode; and

a common electrode disposed over the pixel electrode pattern for forming an electric field with the pixel electrode pattern.

19. The display apparatus of claim 18, wherein a channel area is defined where the oxide semiconductor pattern overlaps the gate electrode, wherein a channel is formed in the channel area when a turn-on voltage is applied to the gate electrode, said channel having a higher carrier mobility than a channel formed in a silicon layer.

20. The display apparatus of claim 18, wherein the drain electrode covers a portion of the pixel electrode pattern and the oxide semiconductor pattern between the first and second insulating patterns, the second insulating pattern is spaced apart from the gate electrode, and a sidewall of the second insulating pattern is aligned and coplanar with a sidewall of the pixel electrode pattern.