System and Method for Source/Drain Contact Processing

• US 20120211807A1
• Filed: 02/10/2012
• Published: 08/23/2012
• Est. Priority Date: 10/15/2007
• Status: Active Grant

• Current Assignee: Advanced Manufacturing Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: YU, Chen-Hua, HSU, Yu-Rung, CHANG, Cheng-Hung, YEH, Chen-Nan
• Granted Patent: US 11,038,056 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.

Claims

1. A semiconductor device comprising:

a fin on a substrate, the fin having a first height from the substrate and comprising a top surface and a first sidewall; and

a contact in physical connection with both the top surface of the fin and the first sidewall of the fin, the contact extending from the top surface a first distance along the fin towards the substrate, the first distance being less than the first height.

2. The semiconductor device of claim 1, further comprising a second sidewall, the contact being in physical connection with the second sidewall.

3. The semiconductor device of claim 2, further comprising a third sidewall, the contact being in physical connection with the third sidewall.

4. The semiconductor device of claim 1, wherein the fin is part of a non-planar transistor.

5. The semiconductor device of claim 1, wherein the fin comprises a silicide, wherein the contact is in physical connection with the silicide.

6. The semiconductor device of claim 1, further comprising an etch stop layer over the fin, the contact extending through the etch stop layer.

7. The semiconductor device of claim 1, wherein the fin comprises a metal layer, wherein the contact is in physical connection with the metal layer.

8. A semiconductor device comprising:

a conductive semiconductor region on a substrate, the conductive semiconductor region comprising a first surface facing away from the substrate and a second surface extending between the first surface and the substrate;

a dielectric layer overlying the conductive semiconductor region and covering the second surface; and

a contact extending into the dielectric layer and in contact with the first surface and the second surface, wherein a first portion of the dielectric layer is located between a bottom surface of the contact and the substrate.

9. The semiconductor device of claim 8, wherein the conductive semiconductor region further comprises a third surface extending between the first surface and the substrate, the third surface in physical contact with the contact.

10. The semiconductor device of claim 9, wherein the conductive semiconductor region further comprises a fourth surface extending between the first surface and the substrate, the fourth surface in physical contact with the contact.

11. The semiconductor device of claim 8, further comprising a source region, a drain region, and a channel region within the conductive semiconductor region, the channel region located between the source region and the drain region.

12. The semiconductor device of claim 11, wherein the source region and the drain region have a first lattice constant and the channel region has a second lattice constant different from the first lattice constant.

13. The semiconductor device of claim 11, further comprising an etch stop layer over the conductive semiconductor region, the etch stop layer applying stress to the channel region.

14. A semiconductor device comprising:

a fin in contact with a substrate, the fin comprising a semiconductor material; and

a conductive contact making physical contact with multiple sides of the fin, at least one of the multiple sides of the fin being perpendicular to the substrate, the conductive contact not in physical contact with the substrate.

15. The semiconductor device of claim 14, wherein the multiple sides of the fin comprises two sides of the fin.

16. The semiconductor device of claim 14, wherein the multiple sides of the fin comprises three sides of the fin.

17. The semiconductor device of claim 14, wherein the multiple sides of the fin comprises four sides of the fin.

18. The semiconductor device of claim 14, further comprising a gate stack overlying a portion of the fin.

19. The semiconductor device of claim 14, further comprising an interlayer dielectric over the fin, the conductive contact extending into the interlayer dielectric.

20. The semiconductor device of claim 14, wherein the fin comprises a silicide material in physical contact with the conductive contact.