Trench DMOS Transistor with Reduced Gate-to-Drain Capacitance

• US 20120211826A1
• Filed: 02/22/2011
• Published: 08/23/2012
• Est. Priority Date: 02/22/2011
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Leng, Yaojian, Adler, Steven J., Foote, Richard Wendell Jr.
• Granted Patent: US 9,716,167 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance.

Claims

1. A trench DMOS structure comprising:

a semiconductor structure having;

a bottom surface,

a drain region of a first conductivity type that touches the bottom surface,

a body region of a second conductivity type that touches and lies above the drain region,

an opening that extends through the body region into the drain region, the opening having a bottom surface and a side wall surface,

an island of the second conductivity type formed within the drain region that lies directly vertically between and spaced apart from the bottom surface of the semiconductor structure and the bottom surface of the opening, and

a depletion region that touches and completely surrounds the island, the drain region touching and completely surrounding the depletion region.

2. The trench DMOS structure of claim 1 wherein the semiconductor structure further has a source region of the first conductivity type that touches the body region, the drain region and the source region being spaced apart and vertically separated by the body region.

3. The trench DMOS structure of claim 2 and further comprising a gate oxide layer that touches the drain region and the body region to line the side wall surface of the opening.

4. The trench DMOS structure of claim 3 and further comprising a gate that touches the gate oxide layer, the gate being conductive and lying within the opening.

5. The trench DMOS structure of claim 4 and further comprising an insulation region that touches the semiconductor structure over the bottom surface of the opening, and that touches and lies below the gate.

6. A trench DMOS structure comprising:

a semiconductor structure having;

a bottom surface,

a drain region of a first conductivity type that touches the bottom surface,

a body region of a second conductivity type that touches and lies above the drain region,

an opening that extends through the body region into the drain region, the opening having a bottom surface and a side wall surface, and

a first island of the second conductivity type formed within the drain region that lies between and spaced apart from the bottom surface of the semiconductor structure and the bottom surface of the opening;

a first depletion region that touches and completely surrounds the first island, the drain region touching and completely surrounding the first depletion region,

a second island of the second conductivity type formed within the drain region that lies between and spaced apart from the bottom surface of the semiconductor structure and the first island, the first and second islands being vertically aligned, and

a second depletion region that touches and completely surrounds the second island, the drain region touching and completely surrounding the second depletion region.

7. The trench DMOS structure of claim 6 wherein the semiconductor structure further has a source region of the first conductivity type that touches the body region, the drain region and the source region being spaced apart and vertically separated by the body region.

8. The trench DMOS structure of claim 7 and further comprising a gate oxide layer that touches the drain region and the body region to line the side wall surface of the opening.

9. The trench DMOS structure of claim 8 and further comprising a gate that touches the gate oxide layer, the gate being conductive and lying within the opening.

10. The trench DMOS structure of claim 9 and further comprising an insulation region that touches the semiconductor structure over the bottom surface of the opening, and that touches and lies below the gate.

11. A method of forming a trench DMOS structure comprising:

forming an opening in a semiconductor structure of a first conductivity type, the semiconductor structure having a bottom surface, the opening having a side wall surface and a bottom surface that lie above and spaced apart from the bottom surface of the semiconductor structure; and

implanting a dopant through the bottom surface of the opening to form an island of a second conductivity type that lies between and spaced apart from the bottom surface of the semiconductor structure and the bottom surface of the opening.

12. The method of claim 11 and further comprising forming a gate oxide layer on the side wall surface of the opening.

13. The method of claim 12 and further comprising depositing a layer of conductive material that touches the gate oxide layer and lies in the opening.

14. The method of claim 13 wherein the layer of conductive material includes polysilicon.

15. The method of claim 13 and further comprising planarizing the layer of conductive material to form a gate.

16. The method of claim 15 and further comprising implanting the semiconductor structure to form a drain region of the first conductivity type and a body region of the second conductivity type that touches and lies above the drain region.

17. The method of claim 16 and further comprising implanting the semiconductor structure to form a source region of the first conductivity type that touches the body region and lies above and spaced apart from the drain region.

18. The method of claim 17 and further comprising forming an insulation region that touches the bottom surface of the opening.