HYBRID SPLIT GATE SEMICONDUCTOR

• US 20120211828A1
• Filed: 04/30/2012
• Published: 08/23/2012
• Est. Priority Date: 10/21/2009
• Status: Abandoned Application

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Chen, Qufei, Terrill, Kyle, Gao, Yang, Shi, Sharon, Bobde, Madhur, Azam, Misbah Ul
• Application Number:
  US13/460,567
• Publication Number:
  US 20120211828A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In an embodiment in accordance with the present invention, a semiconductor device includes a vertical channel region, a gate at a first depth on a first side of the vertical channel region, a shield electrode at a second depth on the first side of the vertical channel region, and a hybrid gate at the first depth on a second side of the vertical channel region. The region below the hybrid gate on the second side of the vertical channel region is free of any electrodes.

Claims

1. A semiconductor device comprising:

a vertical channel region;

a gate at a first depth on a first side of said vertical channel region;

a shield electrode at a second depth on said first side of said vertical channel region; and

a hybrid gate at said first depth on a second side of said vertical channel region,

wherein the region below said hybrid gate on said second side of said vertical channel region is free of any electrode.

2. The semiconductor device of claim 1 wherein said gate, said shield electrode and said hybrid gate comprise polysilicon.

3. The semiconductor device of claim 1 wherein said gate and said hybrid gate are electrically coupled.

4. The semiconductor device of claim 1 wherein said gate and said shield electrode are physically separated by an oxide.

5. The semiconductor device of claim 1 wherein said and said hybrid gate are physically separated by said vertical channel region.

6. The semiconductor device of claim 1 further comprising a source electrode coupled to said shield electrode.

7. The semiconductor device of claim 1 comprising a trench metal oxide semiconductor field effect transistor (MOSFET) device.

8. A structure comprising:

a first elongated structure disposed beneath a surface of a semiconductor substrate comprising;

a gate structure at a first depth below said surface;

a shield electrode structure at a second depth below said surface; and

a second elongated structure formed beneath said surface comprising a hybrid gate structure at said first depth,

wherein said second elongated structure is free of another electrode.

9. The structure of claim 8 wherein said first and second elongated structures are parallel.

10. The structure of claim 8 wherein said gate structure and said hybrid gate structure are electrically coupled.

11. The structure of claim 8 wherein said gate structure and said shield electrode structure are physically separated by an oxide.

12. The structure of claim 8 wherein said semiconductor substrate is doped to form a body region between said first and second elongated structures.

13. The structure of claim 8 wherein said semiconductor substrate further comprises source regions and a drift region.

14. The structure of claim 8 comprising a trench power metal oxide semiconductor field effect transistor (MOSFET) device.

15. A structure comprising:

a first plurality of first trenches formed in a semiconductor substrate to a first depth; and

a second plurality of second trenches formed in said semiconductor substrate to a second depth,

wherein said first trenches are parallel with said second trenches, and

wherein further said first trenches alternate with said second trenches.

16. The structure of claim 15 wherein said first trenches are filled with first materials comprising a first polysilicon and a second polysilicon, above said first polysilicon.

17. The structure of claim 16 wherein said second trenches are filled with second materials comprising said second polysilicon.

18. The structure of claim 16 wherein said first materials comprise an oxide separating said first polysilicon from said second polysilicon.

19. The structure of claim 15 wherein said semiconductor substrate is doped to form a third plurality of body regions between said first and second trenches.

20. The structure of claim 15 comprising a trench power metal oxide semiconductor field effect transistor (MOSFET) device.