SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT ELEMENTS

• US 20120211837A1
• Filed: 02/14/2012
• Published: 08/23/2012
• Est. Priority Date: 02/17/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Baars, Peter, Schloesser, Till, Jakubowski, Frank, Wei, Andy, Carter, Richard, Schaller, Matthias
• Granted Patent: US 8,835,245 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

When forming sophisticated semiconductor devices, a replacement gate approach may be applied in combination with a self-aligned contact regime by forming the self-aligned contacts prior to replacing the placeholder material of the gate electrode structures.

Claims

1. A method, comprising:

forming a contact element laterally adjacent to a gate electrode structure so as to connect to one of a drain region and source region formed in an active region of a semiconductor device, said gate electrode structure comprising a placeholder electrode material covered by a dielectric cap layer; and

replacing said placeholder electrode material at least with a metal-containing electrode material in the presence of said contact element.

2. The method of claim 1, wherein forming said contact element comprises forming a dielectric material above said drain and source regions and laterally adjacent to said gate electrode structure and forming a contact opening therein so as to expose at least a portion of said one of a drain region and a source region.

3. The method of claim 2, wherein forming said contact element further comprises providing a hard mask above said dielectric material so as to define a lateral shape and position of said contact opening.

4. The method of claim 3, wherein a lateral shape and a lateral position of said contact opening are selected so as to be within lateral boundaries of said active region along a width direction of said active region.

5. The method of claim 2, wherein forming said contact element further comprises forming a sacrificial fill material in said contact opening, and performing a removal process in the presence of said sacrificial fill material so as to expose a surface of said placeholder material.

6. The method of claim 5, wherein forming said contact element further comprises removing said sacrificial fill material in said contact opening and forming a conductive contact material in said contact opening.

7. The method of claim 2, wherein forming said contact element further comprises forming a conductive contact material in said contact opening prior to removing said dielectric cap layer from above said placeholder material.

8. The method of claim 2, wherein forming said contact element further comprises forming a metal silicide in a portion of said one of a drain region and a source region through said contact opening.

9. The method of claim 1, wherein forming said contact element comprises forming a conductive contact material above said drain and source regions, forming an isolation opening in said conductive contact material and forming a dielectric material in said isolation opening so as to laterally isolate said contact element.

10. The method of claim 9, wherein forming said contact element further comprises forming a metal silicide in said drain and source regions prior to forming said conductive contact material.

11. The method of claim 1, further comprising forming a dielectric layer stack above said gate electrode structure and said contact element and forming an interconnect structure in said dielectric layer stack so as to connect to said electrode metal of said gate electrode structure and to said contact element.

12. The method of claim 11, wherein forming said interconnect structure comprises performing a first lithography process so as to determine a lateral shape and position of a first elongated interconnect portion that extends substantially in parallel to said gate electrode structure and performing a second lithography process so as to determine a lateral shape and position of a second interconnect portion that extends substantially perpendicularly to said gate electrode structure.

13. The method of claim 12, wherein the lateral shape and position of said second interconnect portion are determined so as to enable formation of said second interconnect portion partially within lateral boundaries of said active region.

14. A method, comprising:

forming a dielectric layer laterally adjacent to a plurality of gate electrode structures formed above an active region of a semiconductor device;

forming a contact opening in said dielectric material so as to connect to said active region;

forming a contact element in said contact opening; and

replacing a placeholder material of said plurality of gate electrode structures at least with a metal-containing electrode material after forming said contact element.

15. The method of claim 14, further comprising, after forming said contact element, forming a second dielectric layer above said dielectric layer and forming an elongated interconnect portion in said second dielectric layer so as to connect to one or more of said gate electrode structures, wherein said elongated interconnect portion is positioned above said active region so as to be laterally at least partially within said active region.

16. The method of claim 15, wherein forming said contact element comprises determining a lateral shape and position of an exclusion zone that includes a contact area of said one or more gate electrode structures and avoiding forming said contact opening in said exclusion zone.

17. The method of claim 14, further comprising exposing a surface of said placeholder material after forming said contact opening and prior to forming said contact element.

18. The method of claim 14, further comprising exposing a surface of said placeholder material in the presence of said contact element.

19. A semiconductor device, comprising:

a plurality of gate electrode structures formed on an active region, each of said plurality of gate electrode structures comprising a high-k dielectric material, an electrode metal and a dielectric sidewall spacer structure;

a contact element formed laterally between two of said plurality of gate electrode structures in a first dielectric material and connecting to said active region, said contact element being delineated in a length direction by said dielectric spacer structures; and

an interconnect structure formed in a second dielectric material above said first dielectric material, said interconnect structure comprising a first interconnect portion connecting to said contact element and comprising a second interconnect portion connecting to at least one of said plurality of gate electrode structures.

20. The semiconductor device of claim 19, wherein said second interconnect portion is an elongated line portion that is at least partially routed above said active region.