SEMICONDUCTOR PACKAGE HAVING THROUGH SILICON VIA (TSV) INTERPOSER AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

• US 20120211885A1
• Filed: 07/22/2011
• Published: 08/23/2012
• Est. Priority Date: 02/17/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, YunSeok, Lee, ChungSun
• Granted Patent: US 8,928,132 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2221/68331 of passive members, e.g. die mounting substrate
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

A semiconductor package having a reduced size by including an interposer having through substrate vias (TSVs), the semiconductor package may comprise a lower semiconductor package which includes a lower base substrate, an interposer with TSVs on the lower base substrate, and a lower semiconductor chip on the interposer and electrically connected to the interposer. The semiconductor package may include an upper semiconductor package on the lower semiconductor package including an upper semiconductor chip and package connecting members on the interposer and electrically connect the upper semiconductor package to the interposer. An exterior molding member may be provided.

Claims

1. A semiconductor package comprising:

a lower semiconductor package comprising;

an interposer formed of a semiconductor material or a glass material comprising a lower surface, an upper surface, lower terminals on a lower surface, upper terminals on an upper surface and through substrate vias extending through at least a substrate of the interposer and electrically connecting ones of the lower terminals of the interposer to corresponding ones of the upper terminals of the interposer;

a lower semiconductor chip mounted to the interposer, the lower semiconductor chip including chip pads electrically connected to at least some of the upper terminals of the interposer; and

a molding material surrounding sides of the lower semiconductor chip;

an upper semiconductor device stacked on the lower semiconductor package comprising;

a lower surface;

terminals at the lower surface; and

an integrated circuit electrically connected to at least some of the

terminal on the lower surface; and

conductive bumps disposed on the upper surface of the interposer and extending to the lower surface of the upper semiconductor device and electrically connecting ones of the upper terminals on the upper surface of the interposer to corresponding ones of the terminals at the lower surface of the upper semiconductor device, each of the conductive bumps comprising a lower portion and an upper portion.

2. The semiconductor package of claim 1, further comprising:

a passive device comprising terminal pads connected to the conductive bumps.

3. The semiconductor package of claim 2, wherein the passive device comprises at least one of a capacitor, a resistor and an inductor.

4. The semiconductor package of claim 1, further comprising:

a dielectric layer on the lower semiconductor chip; and

a wiring pattern on the dielectric layer,

wherein the upper semiconductor device includes an upper semiconductor package comprising;

an upper package substrate comprising a lower surface, an upper surface, lower terminals on the lower surface, upper terminals on the upper surface in electrical communication with the lower terminals;

an upper semiconductor chip including the integrated circuit mounted to the upper package substrate, the upper semiconductor chip including chip pads electrically connected at least some of the lower terminals of the upper package substrate via the upper terminals; and

wherein the upper portion of each of the conductive bumps is connected to a corresponding lower terminal on the lower surface of the upper package substrate,

wherein the upper portion of each of the conductive bumps is connected to a corresponding lower portion of the conductive bumps.

5. The semiconductor package of claim 4, wherein a size of the upper portion of the conductive bumps is larger than a size of the lower portion of the conductive bumps.

6. The semiconductor package of claim 1, the interposer comprises

a wiring pattern connecting upper terminals of the through substrate vias of the interposer to corresponding chip pads of the lower semiconductor chip.

7. The semiconductor package of claim 1, further comprising:

a printed circuit board including an upper surface and a lower surface; and

package terminals attached to the lower surface of the printed circuit board,

wherein the interposer is mounted to the printed circuit board at the upper surface of the printed circuit board.

8. The semiconductor package of claim 7, wherein the printed circuit board includes a redistribution wiring layer, including a first conductor which is electrically connected to a chip pad of the lower semiconductor chip through a first through substrate via of the interposer and connected to a chip pad of the upper semiconductor chip through a second through substrate via of the interposer, but is not connected to any conductive terminals on the lower surface of the printed circuit board, including not being connected to any of the package terminals on the lower surface of the printed circuit board.

9. The semiconductor package of claim 8, wherein the chip pad of the lower semiconductor chip is a data pad connected to a data buffer of the lower semiconductor chip and the chip pad of the upper semiconductor chip is a data pad connected to a data buffer of the upper semiconductor chip.

10. The semiconductor package of claim 8, wherein the chip pad of the lower semiconductor chip is an address pad connected to an address buffer of the lower semiconductor chip and the chip pad of the upper semiconductor chip is an address pad connected to an address buffer of the upper semiconductor chip.

11. The semiconductor package of claim 8, wherein the chip pad of the lower semiconductor chip is a clock pad connected to a clock buffer of the lower semiconductor chip and the chip pad of the upper semiconductor chip is a clock pad connected to a clock buffer of the upper semiconductor chip.

12. The semiconductor package of claim 7, further comprising a package molding material extending at least from the upper surface of the printed circuit board package substrate to the lower surface of the upper package substrate.

13. The semiconductor package of claim 7, further comprising a homogeneous molding on the exterior surface of the lower package, extending at least from a lower surface of the upper package to the upper surface of the printed circuit board package substrate.

14. The semiconductor package of claim 7, wherein the printed circuit board substrate is 220 um or less.

15. The semiconductor package of claim 7, wherein the printed circuit board substrate includes two wiring redistribution layers or less.

16. The semiconductor package of claim 1, wherein the lower semiconductor chip is mounted to the interposer with a face down configuration.

17. The semiconductor package of claim 16, wherein the conductive bumps are first conductive bumps, wherein the lower semiconductor chip includes chip pads at an active surface of the semiconductor chip facing the interposer, and the semiconductor package further comprises:

second conductive bumps extending from the active surface of the semiconductor chip to the interposer, connecting the chip pads of the lower semiconductor chip to corresponding ones of the upper terminals of the interposer, the second conductive bumps having a height of 20 um or less.

18. The semiconductor package of claim 17, wherein the second conductive bumps directly connect the chip pads of the lower semiconductor chip to corresponding ones of the upper terminals of the interposer.

19. The semiconductor package of claim 1, wherein the lower chip has a first surface facing the upper surface of the interposer and a second surface opposite the first surface, and the package further comprises:

an air gap between the second surface of the lower semiconductor chip and the lower surface of the upper package substrate.

20. The semiconductor package of claim 19, wherein the air gap has a thickness of 50 um or less.

21. The semiconductor package of claim 1, wherein the conductive bumps extend from the upper surface of the interposer to the lower terminals on the lower surface of the upper package substrate.

22. The semiconductor package of claim 21, wherein the conductive bumps have a height of 120 um or less.

23. The semiconductor package of claim 1, wherein the upper surface of the interposer has a root mean square surface roughness less than 1.3 nm.

24. The semiconductor package of claim 1, wherein the interposer includes a wiring redistribution layer.

25. The semiconductor package of claim 24, wherein the wiring redistribution layer includes a redistribution pattern including a first conductor that is electrically isolated from the lower semiconductor chip.

26. The semiconductor package of claim 24, wherein the wiring redistribution layer includes a redistribution pattern having a pitch between at least some of adjacent conductors of the redistribution pattern of 10 um or less.

27. The semiconductor package of claim 24, wherein the wiring redistribution layer includes a redistribution pattern having a pitch between at least some of adjacent conductors of the redistribution pattern of 5 um or less.

28. The semiconductor package of claim 1, wherein the CTE of the interposer is no greater than about twice the CTE of the lower semiconductor chip.

29. The semiconductor package of claim 1, wherein the CTE of the interposer is no greater than about 1.3 times the CTE of the lower semiconductor chip.

30. The semiconductor package of claim 1, wherein the CTE of the interposer is substantially equal to the CTE of the lower semiconductor chip.

31. The semiconductor package of claim 1, wherein the interposer is comprised of silicon, germanium, silicon-germanium, or gallium arsenide.

32. The semiconductor package of claim 1,

wherein a first conductive node comprises a first lower terminal of the interposer, a first through substrate via of the interposer, a first upper terminal of the interposer, a first conductive bump disposed on the interposer, a first lower terminal on the lower surface of the upper package substrate, and a first upper terminal of the upper surface of the upper package substrate, and a Vdd chip pad of the upper semiconductor chip connected to provide a Vdd power supply to an internal power supply circuit of the upper semiconductor chip;

wherein a second conductive node comprises a second lower terminal of the interposer, a second through substrate via of the interposer, a second upper terminal of the interposer, a second conductive bump disposed on the interposer, a second lower terminal on the lower surface of the upper package substrate, a second upper terminal of the upper surface of the upper package substrate, a Vss chip pad of the upper semiconductor chip connected to provide a Vss power supply to the internal power supply circuit of the upper semiconductor chip, and a Vss chip pad of the lower semiconductor chip connected to provide a Vss power supply to an internal power supply circuit of the lower semiconductor chip,

wherein a third conductive node comprises a third lower terminal of the interposer, a third through substrate via of the interposer, and a Vdd chip pad of the lower semiconductor chip connected to provide a Vdd power supply to the internal power supply circuit of the lower semiconductor chip, and

wherein the first conductive node, the second conductive node and the third conductive node are each different from each other,

wherein the first conductive node does not provide a Vdd power supply to the lower semiconductor chip, and

wherein the third conductive node does not provide a Vdd power supply to the upper semiconductor chip.

33. The semiconductor package of claim 1, wherein a bulk material of the interposer is composed of a rigid material having a Young'"'"'s modulus of 100 GPa or more.

34. A semiconductor package comprising:

an upper semiconductor package; and

a lower semiconductor package, the upper semiconductor package being stacked on the lower semiconductor package,

wherein the lower package comprises;

an interposer formed of a semiconductor material or a glass material comprising a lower surface, an upper surface, lower terminals on a lower surface, upper terminals on an upper surface and through substrate vias extending through at least a substrate of the interposer and electrically connecting respective ones of the lower terminals of the interposer to ones of the upper terminals of the interposer;

a lower semiconductor chip mounted to the interposer, the lower semiconductor chip including chip pads electrically connected to at least some of the upper terminals of the interposer;

conductive bumps disposed on the upper surface of the interposer adjacent to the lower semiconductor chip and electrically connected to at least some of the upper terminals of the interposer;

a molding material surrounding sides of the lower semiconductor chip, wherein the upper semiconductor package comprises;

an upper package substrate comprising a lower surface, an upper surface, lower terminals on the lower surface, upper terminals on the upper surface in electrical communication with the lower terminals, the lower terminals of the upper base substrate being electrically connected to the conductive bumps; and

an upper semiconductor chip mounted to the upper package substrate, the upper semiconductor chip including chip pads electrically connected to at least some of the upper terminals of the upper package substrate.

36. The package of claim 34, wherein the entire uppermost surface of the molding material and the entire uppermost surface of the lower chip lie within 5 um of a first plane.

37. The package of claim 34, wherein an upper surface of the molding material is flush with an upper surface of the lower semiconductor chip.

38. The package of claim 34,

wherein at least some of the conductive bumps are regularly spaced with a pitch of 0.4 mm or less.

39. The package of claim 34,

wherein the lower chip has a first surface facing the upper surface of the interposer and a second surface opposite the first surface, and

wherein a distance from the second surface of the lower chip to the upper surface of the interposer is 70 um or less.

35. The package of 34, wherein the upper surface of the molding material is coplanar with the upper surface of the lower semiconductor chip.

40. A semiconductor package comprising:

an upper semiconductor package; and

a lower semiconductor package, the upper semiconductor package being stacked on the lower semiconductor package,

wherein the lower package comprises;

an interposer comprising a lower surface, an upper surface, lower terminals on a lower surface, upper terminals on an upper surface and through substrate vias extending through at least a substrate of the interposer and electrically connecting respective ones of the lower terminals of the interposer to ones of the upper terminals of the interposer;

a lower semiconductor chip mounted to the interposer, the lower semiconductor chip including chip pads electrically connected to at least some of the upper terminals of the interposer, the lower chip having a thickness of 50 um or less;

conductive bumps disposed on the upper surface of the interposer adjacent to the lower semiconductor chip and electrically connected to at least some of the upper terminals of the interposer;

wherein the upper semiconductor package comprises;

an upper package substrate comprising a lower surface, an upper surface, lower terminals on the lower surface, upper terminals on the upper surface in electrical communication with the lower terminals, the lower terminals of the upper base substrate being electrically connected to the conductive bumps; and

an upper semiconductor chip mounted to the upper package substrate, the upper semiconductor chip including chip pads electrically connected to at least some of the upper terminals of the upper package substrate.

41-49. -49. (canceled)