Smart clamp
First Claim
1. A circuit comprising:
- a transistor having a source, a gate and a drain, the transistor having a drain-to-source voltage VDS, the transistor having a gate-to-source voltage VGS; and
a clamp and control circuit that;
(1) in a first mode drives the gate of the transistor such that the transistor is off provided VDS does not exceed a voltage A, (2) in a second mode drives the transistor such that the transistor is on, and (3) in a third mode drives the gate of the transistor such that the transistor operates in its linear region if VDS exceeds a voltage B but is off if VDS is less than B, wherein A is greater than B.
1 Assignment
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Accused Products
Abstract
In a circuit that turns off a fluorescent lamp, clamping circuitry is provided to dissipate energy stored in a ballast when the lamp is being turned off. In a normal state in which the lamp is on, or in a normal state in which the lamp is off, clamping is not performed as long the VDS of a power switch is below a voltage A. In a lamp turn off operation, the switch is turned on for a time period to extinguish the lamp, and is then made to operate as a clamp (operate in its linear region) for a second period of time to dissipate energy that was stored in the ballast. Clamping in the linear region continues for VDS voltages down to B as ballast energy is dissipated, where B is smaller than A. By clamping down to the lower voltage B, re-ignition of the lamp is prevented.
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Citations
26 Claims
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1. A circuit comprising:
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a transistor having a source, a gate and a drain, the transistor having a drain-to-source voltage VDS, the transistor having a gate-to-source voltage VGS; and a clamp and control circuit that;
(1) in a first mode drives the gate of the transistor such that the transistor is off provided VDS does not exceed a voltage A, (2) in a second mode drives the transistor such that the transistor is on, and (3) in a third mode drives the gate of the transistor such that the transistor operates in its linear region if VDS exceeds a voltage B but is off if VDS is less than B, wherein A is greater than B. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A circuit, comprising:
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a power switch having a source, a gate and a drain; a voltage translation and gate drive circuit coupled to the gate of the power switch; and a clamp circuit coupled between the drain of the power switch and the gate of the power switch, wherein the clamp circuit comprises; a first zener diode; a second zener diode coupled in series with the first zener diode; and a transistor coupled in parallel with the second zener diode. - View Dependent Claims (12, 13, 14)
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15. A method comprising:
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(a) driving a gate of a power switch in a first mode such that the power switch is off provided a drain-to-source voltage VDS of the power switch does not exceed a voltage A; (b) driving the gate of the power switch in a second mode such that the power switch is on; and (c) driving the gate of the power switch in a third mode such that the power switch operates in its linear region if VDS exceeds a voltage B but is off if VDS is less than B, wherein A is greater than B. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A circuit comprising:
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a power transistor having a source, a gate and a drain, the power transistor having a drain-to-source voltage VDS, the power transistor having a gate-to-source voltage VGS; and means for driving the power transistor such that;
(1) in a first mode the power transistor is off provided VDS does not exceed a voltage A, (2) in a second mode the power transistor is on, and (3) in a third mode the power transistor operates in its linear region if VDS exceeds a voltage B but is off if VDS is less than B, wherein A is greater than B. - View Dependent Claims (22, 23)
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24. A circuit comprising:
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a rectifier; a power switch coupled to the rectifier, wherein the power switch has a drain and a gate; and a clamp circuit that is coupled to the drain and that is coupled to the gate, wherein the clamp circuit comprises; a first zener diode; a second zener diode coupled in series with the first zener diode; and a transistor coupled in parallel with the second zener diode. - View Dependent Claims (25, 26)
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Specification