Logic Circuit, Integrated Circuit Including The Logic Circuit, And Method Of Operating The Integrated Circuit

• US 20120212255A1
• Filed: 09/23/2011
• Published: 08/23/2012
• Est. Priority Date: 02/21/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeong, Hyung-su, Kim, Ho-jung, Choi, Hyun-sik
• Granted Patent: US 8,604,827 B2
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: H03K 19/1733 Controllable logic circuits H03K19/177 takes precedence

Abstract

The logic circuit includes at least one variable resistance device configured such that a resistance value of the at least one variable resistance device varies according to at least one selected value. The selected value is selected from among a voltage and a current of an input signal, and the at least one variable resistance device is configured to memorize the resistance value. The logic circuit is configured to store multi-level data by setting the memorized resistance value.

Claims

1. A logic circuit comprising:

at least one variable resistance device configured such that a resistance value of the at least one variable resistance device varies according to at least one selected value, the selected value being selected from among a voltage and a current of an input signal, the at least one variable resistance device being configured to memorize the resistance value,

wherein the logic circuit is configured to store multi-level data by setting the memorized resistance value.

2. The logic circuit of claim 1, wherein the input signal is a multi-bit signal.

3. The logic circuit of claim 1, further comprising:

a write unit including the at least one variable resistance device, the write unit being configured to write the multi-level data to the variable resistance device by setting the resistance value of the at least one variable resistance device based on the at least one selected value and a write enable signal; and

a read unit configured to read the multi-level data corresponding to the set resistance value of the at least one variable resistance and a read enable signal.

4. The logic circuit of claim 3, wherein, the write unit is configured such that if the write enable signal is activated, a current flowing through the at least one variable resistance device varies according to the at least one selected value.

5. The logic circuit of claim 3, wherein the write unit comprises:

a first write switch connected between a first power supply voltage terminal and a first node, and configured to be switched on based on an inverted signal of the write enable signal;

a current supply unit connected between the first node and a second node, and configured to be switched on and to supply a write current to the second node based on the input signal;

the at least one variable resistance device being connected between the second node and a third node; and

a second write switch connected between the third node and a ground voltage terminal, and configured to be switched on based on the write enable signal.

6. The logic circuit of claim 5, wherein, the read unit is configured such that if the read enable signal is activated, the read unit reads the multi-level data corresponding to the set resistance value of the at least one variable resistance device by sensing a voltage of the second node.

7. The logic circuit of claim 6, wherein the read unit comprises:

a first read switch connected between a second power supply voltage terminal and a fourth node, and configured to be switched on according to an inverted signal of the read enable signal;

a bias unit connected between the fourth node and the second node, and configured to be switched on and to supply a read current to the second node according to a bias signal; and

a second read switch connected between the third node and the ground voltage terminal, and configured to be switched on according to the read enable signal.

8. The logic circuit of claim 7, wherein the current supply unit includes a current supply switch, the bias unit includes a bias switch, and the current supply switch is larger than the bias switch.

9. The logic circuit of claim 7, wherein the bias unit comprises a bias switch,

wherein a size of the bias switch is configured such that the bias switch does not to influence the set resistance value of the at least one variable resistance device.

10. The logic circuit of claim 5, wherein, the read unit is configured such that if the read enable signal is activated, the read unit reads the multi-level data corresponding to the set resistance value of the at least one variable resistance device by sensing a voltage of the third node.

11. The logic circuit of claim 10, wherein the read unit comprises:

a first read switch connected between a second power supply voltage terminal and the second node, and configured to be switched on based on an inverted signal of the read enable signal;

a bias unit connected between the third node and a fourth node, and configured to be switched on and to supply a read current to the third node based on a bias signal; and

a second read switch connected between the fourth node and the ground voltage terminal, and configured to be switched on based on the read enable signal.

12. The logic circuit of claim 11, wherein the current supply unit includes a current supply switch, the bias unit includes a bias switch, and the current supply switch is larger than the bias switch.

13. The logic circuit of claim 11, wherein the bias unit includes a bias switch, and a size of the bias switch is determined not to influence the resistance value written to the at least one variable resistance device.

14. The logic circuit of claim 3, wherein the write unit comprises:

an input signal receiving unit connected between a first power supply voltage terminal and a plurality of input nodes, the input signal receiving unit being configured to activate one of the plurality of input nodes according to the input signal;

a first write switching unit connected between the plurality of input nodes and a ground voltage terminal, and configured to be switched on based on an inverted signal of the write enable signal;

a current supply unit connected between a second power supply voltage terminal and a first node, the current supply unit being configured to supply a write current to the first node based on an activated input node from among the plurality of input nodes;

the at least one variable resistance device connected between the first node and a second node; and

a second write switch connected between the second node and the ground voltage terminal, and configured to be switched on based on the write enable signal.

15. The logic circuit of claim 14, wherein the current supply unit comprises:

a plurality of switches commonly connected to the second power supply voltage terminal, and configured to be switched on based on voltages of the plurality of input nodes, respectively; and

a plurality of current adjustment devices connected in series to the plurality of switches, respectively, and configured to be switched on based on a first bias signal,

wherein sizes of the plurality of current adjustment devices are different from one another.

16. The logic circuit of claim 14, wherein the current supply unit comprises:

a plurality of current adjustment devices commonly connected to the second power supply voltage terminal, and configured to be switched on according to voltages of the plurality of input nodes, respectively,

wherein sizes of the plurality of current adjustment devices are different from one another.

17. The logic circuit of claim 14, wherein the read unit is configured such that if the read enable signal is activated, the read unit reads the multi-level data corresponding to the set resistance value of the at least one variable resistance device by sensing a voltage of the first node.

18. The logic circuit of claim 17, wherein the read unit comprises:

a first read switch connected between a third power supply voltage terminal and a third node, and configured to be switched on based on an inverted signal of the read enable signal;

a bias unit connected between the third node and the first node, and configured to be switched on and to supply a read current to the first node based on a bias signal; and

a second read switch connected between the second node and the ground voltage terminal, and configured to be switched on based on the read enable signal.

19. The logic circuit of claim 18, wherein the read unit further comprises a sense amplifier configured to generate a determination based on the voltage of the first node and a plurality of reference voltages that are different from one another, and to read the multi-level data based on the determination.

20. The logic circuit of claim 18, wherein the bias unit comprises:

a bias switch, a size of the bias switch being configured such that the bias switch does not influence the set resistance value of the at least one variable resistance device.

21. The logic circuit of claim 14, wherein, the read unit is configured such that if the read enable signal is activated, the read unit reads the multi-level data corresponding to the set resistance value of the at least one variable resistance device by sensing a voltage of the second node.

22. The logic circuit of claim 21, wherein the read unit comprises:

a first read switch connected between a third power supply voltage terminal and the first node, and configured to be switched on based on an inverted signal of the read enable signal;

a bias unit connected between the second node and a third node, and configured to be switched on based on a bias signal to supply a read current to the second node; and

second read switch connected between the third node and the ground voltage terminal, and configured to be switched on based on the read enable signal.

23. The logic circuit of claim 22, wherein the read unit further comprises:

a sense amplifier configured to generate a determination based on the voltage of the second node and a plurality of reference voltages that are different from one another to read the multi-level data based on the determination.

24. The logic circuit of claim 22, wherein the bias unit comprises:

a bias switch, a size of the bias switch being configured such that the bias switch does not to influence the set resistance value of the at least one variable resistance device.

25. The logic circuit of claim 3, wherein the write enable signal and the read enable signal are synchronized with a clock signal.

26. The logic circuit of claim 1, wherein the at least one variable resistance device includes at least one of a memristor and a resistive memory device.

27. An integrated circuit comprises:

a controller configured to produce a write enable signal and a read enable signal;

a write unit configured to receive the write enable signal; and

a read unit configured to receive the read enable signal,

wherein the write unit includes at least one variable resistance device configured such that a resistance value of the at least one variable resistance device varies according to at least one selected value, the selected value being selected from among a voltage and current of an input signal, the at least one variable resistance device being configured to memorize the resistance value, the write unit being configured to write multi-level data to the at least one variable resistance device by setting the resistance value based on the write enable signal, and

wherein the read unit is configured to read the multi-level data corresponding to the set resistance value of the at least one variable resistance device, based on the read enable signal.

28. The logic circuit of claim 27, wherein the controller is configured to produce the write enable signal and the read enable signal in synchronization with a clock signal.

29. A method of operating a logic circuit that includes at least one variable resistance device that memorizes a resistance value, the resistance value varying according to at least one selected value, the selected value being selected from among a voltage and a current of an input signal, the method comprising:

setting the resistance value of the at least one variable resistance device based on the at least one selected value to, if a write enable signal is activated; and

reading multi-level data corresponding to the set resistance value of the at least one variable resistance device by sensing the resistance value, if a read enable signal is activated.

30. The method of claim 29, wherein the setting of the resistance value to the at least one variable resistance device comprises:

supplying a write current to the at least one variable resistance device,

wherein the write current is determined based on the at least one selected value.

31. The method of claim 29, wherein the reading of the multi-level data corresponding to the resistance value comprises:

supplying a read current to the at least one variable resistance device,

wherein the read current is selected such that the read current does not influence the set resistance value of the at least one variable resistance device.