LEVEL SHIFTER

• US 20120212281A1
• Filed: 02/16/2012
• Published: 08/23/2012
• Est. Priority Date: 02/18/2011
• Status: Active Grant

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Ryu, Beom-seon, Lim, Gyu-ho
• Granted Patent: US 8,497,726 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit
• CPC Class Codes: H03K 3/356182 with additional means for controlling the main nodes

Abstract

A level shifter is provided. The level shifter includes a signal converter connected to an external power source and a ground, first and second output terminals connected to the signal converter, the first and second output terminals being configured to output a bias voltage applied from the external power source, and a switching unit configured to switch a connection state of the signal converter according to an input signal to adjust output voltage values of the first and second output terminals, the switching unit including first and second transistors, the first transistor being of a type that is different from a type of the second transistor, the first and second transistors being connected to each other in series between an input terminal, to which an input signal is applied, and the external power source, gates of the first and second transistors being commonly connected to the second output terminal.

Claims

1. A level shifter, comprising:

a signal converter connected to an external power source and a ground;

first and second output terminals connected to the signal converter, the first and second output terminals being configured to output a bias voltage applied from the external power source; and

a switching unit configured to switch a connection state of the signal converter according to an input signal to adjust output voltage values of the first and second output terminals, the switching unit comprising;

first and second transistors, the first transistor being of a type that is different from a type of the second transistor, the first and second transistors being connected to each other in series between an input terminal, to which an input signal is applied, and the external power source, gates of the first and second transistors being commonly connected to the second output terminal; and

a third transistor disposed between the input terminal and the first output terminal, a gate of the third transistor being connected to a first connection node disposed between the first and second transistors.

2. The level shifter as claimed in claim 1, wherein:

if the input signal applied to the input terminal is a high level input signal, the first transistor is turned on; and

if the input signal applied to the input terminal is a low level input signal, the third transistor is turned on.

3. The level shifter as claimed in claim 1, wherein the first transistor is a p-type metal oxide semiconductor (PMOS) transistor, and the second and third transistors are n-type metal oxide semiconductor (NMOS) transistors.

4. The level shifter as claimed in claim 1, wherein the signal converter comprises:

fourth and fifth transistors disposed to make a pair and commonly connected to the external power source;

a sixth transistor connected between the fourth transistor and the ground, the third transistor being disposed between a second connection node, disposed between the fourth and sixth transistors, and the input terminal, the second connection node being connected to the first output terminal, the gates of the first and second transistors being commonly connected to a gate of the sixth transistor; and

a seventh transistor connected between the fifth transistor and the ground and to the input terminal, a third connection node, disposed between the fifth and seventh transistors, being connected to the second output terminal.

5. The level shifter as claimed in claim 4, wherein the fourth and fifth transistors are PMOS transistors, and the sixth and seventh transistors are NMOS transistors.

6. The level shifter as claimed in claim 1, wherein the first and second output terminals respectively comprise inverters that invert and output a bias voltage applied from the external power source.

7. A level shifter, comprising:

first and second transistors connected to each other in series between an input terminal, to which an input signal is applied, and an external power source, the first transistor being of a type that is different from a type of the second transistor;

a third transistor comprising a gate connected to a first connection node disposed between the first and second transistors;

fourth and fifth transistors disposed to make a pair and commonly connected to the external power source;

a sixth transistor connected between the fourth transistor and a ground, the third transistor being disposed between a second connection node, disposed between the fourth and sixth transistors, and the input terminal, the second connection node being connected to a first output terminal, the gates of the first and second transistors being commonly connected to a gate of the sixth transistor; and

a seventh transistor connected between the fifth transistor and the ground and to the input terminal, a third connection node disposed between the fifth and seventh transistors being connected to a second output terminal.

8. The level shifter as claimed in claim 7, wherein:

the first, fourth, and fifth transistors are PMOS transistors; and

the second, third, sixth, and seventh transistors are NMOS transistors.

9. The level shifter as claimed in claim 7, wherein the first and second output terminals respectively comprise inverters that invert and output a bias voltage applied from the external power source.