PIXEL CIRCUIT AND DISPLAY APPARATUS

• US 20120212521A1
• Filed: 07/22/2010
• Published: 08/23/2012
• Est. Priority Date: 10/29/2009
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Yamauchi, Yoshimitsu, Ueda, Naoki, Nakano, Fumiki
• Granted Patent: US 8,310,638 B2
• Time in Patent Office: Days
• US Class Current: 345/690
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G09G 2300/0465 Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
• CPC Class Codes: G09G 2300/0876 Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
• CPC Class Codes: G09G 2300/089 Pixel comprising a non-linear two-terminal element in series with each display pixel element, the series comprising also other elements
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Abstract

Disclosed is a display device that can achieve a reduction of power consumption without deteriorating the aperture ratio. A liquid crystal capacitance element (Clc) is formed by being sandwiched between a pixel electrode (20) and an opposite electrode (80). The pixel electrode (20), one end of a first switching circuit (22), one end of a second switching circuit (23), and the first terminal of a second transistor (T2) form an internal node (N1). The other end of the first switching circuit (22) and the other end of the second switching circuit (23) are connected to a source line (SL). The second switching circuit (23) includes a series circuit of a transistor (T1) and a diode (D1), and an output node (N2) is formed of the control terminal of the transistor (T1), the second terminal of the transistor (T2), and one end of a boost capacitance element (Cbst). The other end of the boost capacitance element (Cbst) is connected to a boost line (BST), and the control terminal of the transistor (T2) is connected to a reference line (REF). The diode (D1) has a rectifying function in the direction to the internal node (N1) from the source line (SL).

Claims

1. :

A pixel circuit, comprising;

a display element unit that includes a unit display element;

an internal node constituting a part of the display element unit, the internal node holding a pixel data voltage applied to the display element unit;

a first switching circuit that transfers the pixel data voltage supplied by a data signal line to the internal node through at least a prescribed switching element;

a second switching circuit that transfers the pixel data voltage supplied by the data signal line to the internal node without passing through the prescribed switching element; and

a control circuit that holds, at one end of a first capacitance element, a prescribed voltage corresponding to the pixel data voltage held by the internal node, the control circuit controlling a conducting and non-conducting state of the second switching circuit,

wherein the second switching circuit includes a series circuit of a first transistor element and a diode element, the first transistor element having a first terminal, a second terminal, and a control terminal that controls electrical continuity between the first and second terminals,

wherein the control circuit includes a series circuit of a second transistor element and the first capacitance element, the second transistor element having a first terminal, a second terminal, and a control terminal that controls electrical continuity between the first and second terminals,

wherein respective one ends of the first and second switching circuits are connected to the data signal line,

wherein respective other ends of the first and second switching circuits and the first terminal of the second transistor element are connected to the internal node,

wherein the diode element serves as a rectifier in a direction from the data signal line to the internal node,

wherein the control terminal of the first transistor element, the second terminal of the second transistor element, and the one end of the first capacitance element are connected to each other, forming an output node of the control circuit,

wherein the control terminal of the second transistor element is connected to a first control line, and

wherein another end of the first capacitance element is connected to a second control line.

2. :

The pixel circuit according to claim 1, wherein the prescribed switching element is a third transistor element that has a first terminal, a second terminal, and a control terminal that controls electrical continuity between the first and second terminals, and

wherein the control terminal of the third transistor element is connected to a scanning signal line.

3. :

The pixel circuit according to claim 1, wherein the second switching circuit includes a series circuit of the first transistor element, the diode element, and a fourth transistor element that has a first terminal, a second terminal, and a control terminal that controls electrical continuity between the first and second terminals, and

wherein the control terminal of the fourth transistor element is connected to the second control line or a third control line.

4. :

The pixel circuit according to claim 3, wherein the first switching circuit includes a series circuit of the fourth transistor element in the second switching circuit and the prescribed switching element, or a series circuit of a fifth transistor element and the prescribed switching element, the fifth transistor element having a control terminal thereof connected to the control terminal of the fourth transistor element in the second switching circuit.

5. :

The pixel circuit according to claim 1, further comprising a second capacitance element having one end connected to the internal node and another end connected to a fourth control line or a prescribed fixed voltage line.

6. :

A display device, comprising;

a pixel circuit array in which a plurality of pixel circuits set forth in claim 1 are arranged in a row direction and a column direction, respectively,

wherein the data signal line is provided in each column,

wherein the pixel circuits arranged in a same column have respective one ends of the first switching circuits thereof connected to the same data signal line,

wherein the pixel circuits arranged in a same row or in a same column have the respective control terminals of the second transistor elements thereof connected to the same first control line,

wherein the pixel circuits arranged in the same row or in the same column have the respective other ends of the first capacitance elements connected to the same second control line, and

wherein the display device further comprises a data signal line driver circuit for driving the data signal lines individually, and a control line driver circuit for driving the first and second control lines individually.

7. :

The display device according to claim 6, wherein the prescribed switching element is a third transistor element that has a first terminal, a second terminal, and a control terminal that controls electrical continuity between the first and second terminals, the control terminal being connected to a scanning signal line,

wherein the scanning signal line is arranged in each row,

wherein the pixel circuits arranged in the same row are connected to the same scanning signal line, and

wherein the display device further comprises a scanning signal line driver circuit for driving each scanning signal line individually.

8. :

The display device according to claim 7, wherein the second switching circuit includes a series circuit of the first transistor element, the diode element, and a fourth transistor element, the fourth transistor element having a first terminal, a second terminal, and a control terminal that controls electrical continuity between the first and second terminals, and

wherein the respective pixel circuits arranged in the same row or the same column have the control terminals of the fourth transistor elements thereof connected to the same second control line, respectively.

9. :

The display device according to claim 7, wherein the second switching circuit includes a series circuit of the first transistor element, the diode element, and a fourth transistor element, the fourth transistor element having a first terminal, a second terminal, and a control terminal that controls electrical continuity between the first and second terminals,

wherein the respective pixel circuits arranged in the same row or the same column have the control terminals of the fourth transistor elements thereof connected to a same third control line, respectively, and

wherein the control line driver circuit drives the respective first through third control lines individually.

10. :

The display device according to claim 8, wherein the first switching circuit includes a series circuit of the fourth transistor element in the second switching circuit and the third transistor element, or a series circuit of a fifth transistor element and the third transistor element, the fifth transistor element having a control terminal thereof connected to the control terminal of the fourth transistor element in the second switching circuit.

11. :

The display device according to claim 9, wherein the first switching circuit includes a series circuit of the fourth transistor element in the second switching circuit and the third transistor element, or a series circuit of a fifth transistor element and the third transistor element, the fifth transistor element having a control terminal thereof connected to the control terminal of the fourth transistor element in the second switching circuit.

12. :

The display device according to claim 7, wherein;

when a writing operation for writing the pixel data in the respective pixel circuits arranged in one selected row is performed,

the scanning signal line driver circuit applies a prescribed selected row voltage to the scanning signal line of the selected row so as to turn on the third transistor elements arranged in the selected row, and applies a prescribed non-selected row voltage to the scanning signal lines of non-selected rows so as to turn off the third transistor elements arranged in the non-selected rows, and

the data signal line driver circuit applies, to the respective data signal lines, data voltages corresponding to the pixel data that are to be written in the pixel circuits in the respective columns of the selected row, respectively.

13. :

The display device according to claim 12, wherein, in the writing operation, the control line driver circuit applies, to the first control line, a prescribed voltage that turns on the second transistor element.

14. :

The display device according to claim 10, wherein;

when a writing operation for writing the pixel data in the respective pixel circuits arranged in one selected row is performed,

the scanning signal line driver circuit applies a prescribed selected row voltage to the scanning signal line of the selected row so as to turn on the third transistor elements arranged in the selected row, and applies a prescribed non-selected row voltage to the scanning signal lines of non-selected rows so as to turn off the third transistor elements arranged in the non-selected rows,

the control line driver circuit applies, to the second control line of the selected row, a prescribed select voltage that turns on the fourth transistor element, and applies, to the second control lines of the non-selected rows, a prescribed non-select voltage that turns off the fourth transistor element, and

the data signal line driver circuit applies, to the respective data signal lines, data voltages corresponding to the pixel data that are to be written in the pixel circuits in the respective columns of the selected row, respectively.

15. :

The display device according to claim 11, wherein;

when a writing operation for writing the pixel data in the respective pixel circuits arranged in one selected row is performed,

the scanning signal line driver circuit applies a prescribed selected row voltage to the scanning signal line of the selected row so as to turn on the third transistor elements arranged in the selected row, and applies a prescribed non-selected row voltage to the scanning signal lines of non-selected rows so as to turn off the third transistor elements arranged in the non-selected rows,

the control line driver circuit applies, to the third control line of the selected row, a prescribed select voltage that turns on the fourth transistor element, and applies, to the third control lines of the non-selected rows, a prescribed non-select voltage that turns off the fourth transistor element, and

the data signal line driver circuit applies, to the respective data signal lines, data voltages corresponding to the pixel data that are to be written in the pixel circuits in the respective columns of the selected row, respectively.

16. :

The display device according to claim 7, wherein the internal node of each pixel circuit in the pixel circuit array is configured to be capable of holding one voltage state among a plurality of voltage states that are mutually different to achieve a multi-gradation display,

wherein, in a self-refresh operation that activates the second switching circuits and the control circuits in a plurality of pixel circuits so as to simultaneously compensate voltage changes in the internal nodes thereof, the display device performs a refresh operation for the pixel circuits that have the internal node in a voltage state of a target gradation level as follows;

the scanning signal line driver circuit applies a prescribed voltage to the scanning signal lines connected to all of the pixel circuits in the pixel circuit array so as to turn the third transistor elements off;

the data signal line driver circuit applies a refresh input voltage to the data signal lines, the refresh input voltage being a sum of a refresh target voltage and a prescribed first adjusting voltage, the refresh target voltage corresponding to a voltage state of a target gradation level for which the refresh operation is performed, the prescribed first adjusting voltage corresponding to a turn-on voltage of the second switching circuit; and

the control line driver circuit applies a boost voltage of a prescribed amplitude to the second control line while applying a refresh reference voltage to the first control line so as to change a voltage of the output node by capacitance-coupling through the first capacitance element, the refresh reference voltage being a sum of a refresh isolation voltage and a prescribed second adjusting voltage, the refresh isolation voltage being defined by an intermediate voltage between a voltage state that is one level lower than the target gradation level and a voltage state of the target gradation level, the prescribed second adjusting voltage corresponding to a threshold voltage of the control circuit between the first control line and the internal node, so that;

when the voltage state of the internal node is higher than the refresh target voltage, the diode element becomes reverse-biased in a direction from the data signal line to the internal node, thereby breaking electrical continuity between the data signal line and the internal node,

when the voltage state of the internal node is lower than the refresh isolation voltage, the potential change of the output node by the application of the boost voltage is suppressed, and the first transistor element is turned off, thereby breaking the electrical continuity between the data signal line and the internal node, and

when the voltage state of the internal node is at least the refresh isolation voltage and no more than the refresh target voltage, the diode element becomes forward-biased in a direction from the data signal line to the internal node, and the potential change in the output node is not suppressed, which turns the first transistor element on, thereby providing the refresh target voltage to the internal node.

17. :

The display device according to claim 9, wherein the internal node of each pixel circuit in the pixel circuit array is configured to be capable of holding one voltage state among a plurality of voltage states that are mutually different to achieve a multi-gradation display,

wherein, in a self-refresh operation that activates the second switching circuits and the control circuits in a plurality of pixel circuits so as to simultaneously compensate voltage changes in the internal nodes thereof, the display device performs a refresh operation for the pixel circuits that have the internal node in a voltage state of a target gradation level as follows;

the scanning signal line driver circuit applies a prescribed voltage to the scanning signal lines connected to all of the pixel circuits in the pixel circuit array so as to turn off the third transistor elements;

the data signal line driver circuit applies a refresh input voltage to the data signal lines, the refresh input voltage being a sum of a refresh target voltage and a prescribed first adjusting voltage, the refresh target voltage corresponding to a voltage state of a target gradation level for which the refresh operation is performed, the prescribed first adjusting voltage corresponding to a turn-on voltage of the second switching circuit;

the control line driver circuit applies a boost voltage of a prescribed amplitude to the second control line, while applying a refresh reference voltage to the first control line and applying the a prescribed voltage to the third control line so as to turn on the fourth transistor element, so as to change a voltage of the output node by capacitance-coupling through the first capacitance element, the refresh reference voltage being a sum of a refresh isolation voltage and a prescribed second adjusting voltage, the refresh isolation voltage being defined by an intermediate voltage between a voltage state that is one level lower than the target gradation level and a voltage state of the target gradation level, the prescribed second adjusting voltage corresponding to a threshold voltage of the control circuit between the first control line and the internal node, so that;

when the voltage state of the internal node is higher than the refresh target voltage, the diode element becomes reverse-biased in a direction from the data signal line to the internal node, thereby breaking electrical continuity between the data signal line and the internal node,

when the voltage state of the internal node is lower than the refresh isolation voltage, the potential change of the output node by the application of the boost voltage is suppressed, and the first transistor element is turned off, thereby breaking the electrical continuity between the data signal line and the internal node, and

when the voltage state of the internal node is at least the refresh isolation voltage and no more than the refresh target voltage, the diode element becomes forward-biased in the direction from the data signal line to the internal node, and the potential change in the output node is not suppressed, which turns the first transistor element on, thereby providing the refresh target voltage to the internal node.

18. :

The display device according to claim 16, wherein the refresh operation is sequentially performed for the pixel circuits that respectively have the internal nodes in voltage states of different gradation levels by repeatedly conducting the following operation while changing values of the refresh input voltage and the refresh isolation voltage each time;

applying the boost voltage to the second control line while turning the third transistor element off, and applying the refresh input voltage and the refresh reference voltage to the date signal line and the first control line, respectively.

19. :

The display device according to claim 18, wherein an application of the boost voltage is performed while changing values of the refresh input voltage and the refresh isolation voltage a certain number of times that is one less than the number of gradation levels, the number of gradation levels being the number of voltage states that can be held by the internal node of each pixel circuit in the pixel circuit array.

20. :

The display device according to claim 18, wherein;

after a completion of a refresh step that includes said operation of repeatedly conducting an operation of turning the third transistor element off, applying the refresh input voltage and the refresh reference voltage to the date signal line and the first control line, respectively, and applying the boost voltage to the second control line, while changing values of the refresh input voltage and the refresh isolation voltage each time,

the display device performs a stand-by step in which;

the data signal line driver circuit applies a voltage that corresponds to a smallest value of a voltage state that can be held by the internal node to the data signal line; and

the control line driver circuit applies a voltage that can turn on the second transistor element regardless of the voltage state of the internal node to the first control line at least for a certain period of time, instead of applying the boost voltage to the second control line.

21. :

The display device according to claim 20, wherein the refresh step is performed again after the stand-by step, the stand-by step being performed for a period of time that is at least ten times as long as the refresh step.

22. :

The display device according to claim 16, wherein the first adjusting voltage is a turn-on voltage of the diode element.

23. :

The display device according to claim 16, wherein the second adjusting voltage is a threshold voltage of the second transistor element.

24. :

The display device according to claim 9, wherein the internal node of each pixel circuit in the pixel circuit array is configured to be capable of holding one voltage state among a plurality of voltage states that are mutually different to achieve a multi-gradation display,

wherein, in a self-refresh operation that activates the second switching circuits and the control circuits in a plurality of pixel circuits so as to simultaneously compensate voltage changes in the internal nodes thereof, the display device performs a refresh operation for the pixel circuits that have the internal node in a voltage state of a target gradation level as follows;

the scanning signal line driver circuit applies a prescribed voltage to the scanning signal lines that are connected to all of the pixel circuits in the pixel circuit array so as to turn the third transistor element off;

the data signal line driver circuit applies a refresh input voltage to the data signal line, the refresh input voltage being a sum of a refresh target voltage and a prescribed first adjusting voltage, the refresh target voltage corresponding to a voltage state of a target gradation level for which the refresh operation is performed, the prescribed first adjusting voltage corresponding to a turn-on voltage of the second switching circuit;

the control line driver circuit applies a boost voltage of a prescribed amplitude to the second control line while applying a refresh reference voltage to the first control line so as to change a voltage of the output node by capacitance-coupling through the first capacitance element, the refresh reference voltage being a sum of a refresh isolation voltage and a prescribed second adjusting voltage, the refresh isolation voltage being defined by a voltage intermediate between a voltage state that is one level lower than the target gradation level and a voltage state of the target gradation level, the prescribed second adjusting voltage corresponding to a threshold voltage of the control circuit between the first control line and the internal node; and

the control line driver circuit thereafter applies a prescribed voltage that turns on the fourth transistor element to the third control line, so that;

when the voltage state of the internal node is higher than the refresh target voltage, the diode element becomes reverse-biased in a direction from the data signal line to the internal node, thereby breaking electrical continuity between the data signal line and the internal node,

when the voltage state of the internal node is lower than the refresh isolation voltage, the potential change of the output node by the application of the boost voltage is suppressed, and the first transistor element is turned off, thereby breaking electrical continuity between the data signal line and the internal node, and

when the voltage state of the internal node is at least the refresh isolation voltage and no more than the refresh target voltage, the diode element becomes forward-biased in a direction from the data signal line to the internal node, and the potential change in the output node is not suppressed, which turns the first transistor element on, thereby providing the refresh target voltage to the internal node.

25. :

The display device according to any claim 16, wherein, in the self-refresh operation, a refresh operation is sequentially performed for the pixel circuits that include the internal nodes in voltage states of different gradation levels as follows;

setting a first gradation level as the target gradation and applying the boost voltage to the second control line while applying the refresh input voltage and the refresh reference voltage to the data signal line and the first control line, respectively; and

while continuously applying the boost voltage, setting a second gradation level that is one level higher than the first gradation level as the target gradation level, changing the refresh reference voltage applied to the first control line, and thereafter changing the refresh input voltage applied to the data signal line.

26. :

The display device according to claim 25, wherein;

when there exists a gradation level that is higher than the second gradation level,

after a completion of the refresh operation for the second gradation level,

the display device repeats the refresh operation for the higher gradation level by performing, while continuously applying the boost voltage, setting the target gradation level to a gradation level that is one level higher than the second gradation level, changing the refresh reference voltage applied to the first control line, and thereafter changing the refresh input voltage applied to the data signal line.

27. :

The display device according to claim 17, wherein, in the self-refresh operation, a refresh operation is sequentially performed for the pixel circuits that include the internal nodes in voltage states of different gradation levels as follows;

setting a first gradation level as the target gradation level, and while applying the refresh input voltage and the refresh reference voltage to the data signal line and the first control line, respectively, applying the boost voltage to the second control line and a prescribed voltage that turns on the fourth transistor element to the third control line, respectively; and

while continuously applying the boost voltage and the prescribed voltage that turns on the fourth transistor element, setting the target gradation level to a second gradation level that is one level higher than the first gradation level, changing the refresh reference voltage applied to the first control line, and thereafter changing the refresh input voltage applied to the data signal line.

28. :

The display device according to claim 27, wherein;

when there exists a gradation level that is even higher than the second gradation level,

after a completion of the refresh operation for the second gradation level,

the display device repeats the refresh operation for the higher gradation level by performing, while continuously applying the boost voltage and the prescribed voltage that turns the fourth transistor element on, setting the target gradation level to a gradation level that is one level higher than the second gradation level, changing the refresh reference voltage applied to the first control line, and thereafter changing the refresh input voltage applied to the data signal line.