PROGRAMMABLE LSI

• US 20120212995A1
• Filed: 01/31/2012
• Published: 08/23/2012
• Est. Priority Date: 02/17/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KUROKAWA, Yoshiyuki
• Granted Patent: US 8,675,382 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters

Abstract

A low-power programmable LSI that can perform configuration (dynamic configuration) at high speed and can quickly start is provided. The programmable LSI includes a plurality of logic elements and a memory element for storing configuration data to be input to the plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements in accordance with the configuration data stored in the configuration memory. The memory element is formed using a storage element including a transistor whose channel is formed in an oxide semiconductor layer and a node set in a floating state when the transistor is turned off.

Claims

1. A semiconductor device comprising:

a logic element; and

a memory element comprising a storage element,

wherein the memory element is configured to store configuration data in the storage element and output the configuration data,

wherein the logic element is configured to receive the configuration data and change a function of the logic element in accordance with the configuration data, and

wherein the storage element comprises a first transistor comprising an oxide semiconductor layer.

2. The semiconductor device according to claim 1,

wherein the storage element comprises a second transistor and a capacitor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein a first terminal of the first transistor is electrically connected to a second wiring,

wherein a second terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein a first terminal of the second transistor is electrically connected to a third wiring,

wherein a second terminal of the second transistor is electrically connected to a fourth wiring,

wherein a first electrode of the capacitor is electrically connected to the gate of the second transistor,

wherein a second electrode of the capacitor is electrically connected to a fifth wiring, and

wherein the memory element is configured to output the configuration data through the fourth wiring.

3. The semiconductor device according to claim 1,

wherein the storage element comprises a second transistor and a capacitor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein a first terminal of the first transistor is electrically connected to a second wiring,

wherein a second terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein a first terminal of the second transistor is electrically connected to a third wiring,

wherein a second terminal of the second transistor is electrically connected to the second wiring,

wherein a first electrode of the capacitor is electrically connected to the gate of the second transistor,

wherein a second electrode of the capacitor is electrically connected to a fourth wiring, and

wherein the memory element is configured to output the configuration data through the second wiring.

4. The semiconductor device according to claim 1,

wherein the storage element comprises a second transistor and a third transistor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein a first terminal of the first transistor is electrically connected to a second wiring,

wherein a second terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein a first terminal of the second transistor is electrically connected to a third wiring,

wherein a second terminal of the second transistor is electrically connected to a first terminal of the third transistor,

wherein a second terminal of the third transistor is electrically connected to a fourth wiring,

wherein a gate of the third transistor is electrically connected to a fifth wiring, and

wherein the memory element is configured to output the configuration data through the fourth wiring.

5. The semiconductor device according to claim 1,

wherein the storage element comprises a second transistor and a third transistor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein a first terminal of the first transistor is electrically connected to a second wiring,

wherein a second terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein a first terminal of the second transistor is electrically connected to a third wiring,

wherein a second terminal of the second transistor is electrically connected to a first terminal of the third transistor,

wherein a second terminal of the third transistor is electrically connected to the second wiring,

wherein a gate of the third transistor is electrically connected to a fourth wiring, and

wherein the memory element is configured to output the configuration data through the second wiring.

6. The semiconductor device according to claim 1,

wherein the storage element comprises a capacitor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein a first terminal of the first transistor is electrically connected to a second wiring, and

wherein a second terminal of the first transistor is electrically connected to a first electrode of the capacitor.

7. The semiconductor device according to claim 1,

wherein the logic element comprises a selection circuit,

wherein the selection circuit comprises a first input terminal, a second input terminal, and an output terminal,

wherein the first input terminal is configured to receive a first voltage,

wherein the second input terminal is configured to receive a second voltage,

wherein the selection circuit is configured to output the first voltage while the configuration data is first data, and

wherein the selection circuit is configured to output the second voltage while the configuration data is second data.

8. A semiconductor device comprising:

a first logic element;

a second logic element;

a selection circuit; and

a memory element comprising a storage element,

wherein the memory element is configured to store configuration data in the storage element and output the configuration data,

wherein the selection circuit is configured to receive the configuration data and change an electrical connection between the first logic element and the second logic element in accordance with the configuration data, and

wherein the storage element comprises a first transistor comprising an oxide semiconductor layer.

9. The semiconductor device according to claim 8,

wherein the storage element comprises a second transistor and a capacitor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein a first terminal of the first transistor is electrically connected to a second wiring,

wherein a second terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein a first terminal of the second transistor is electrically connected to a third wiring,

wherein a second terminal of the second transistor is electrically connected to a fourth wiring,

wherein a first electrode of the capacitor is electrically connected to the gate of the second transistor,

wherein a second electrode of the capacitor is electrically connected to a fifth wiring, and

wherein the memory element is configured to output the configuration data through the fourth wiring.

10. The semiconductor device according to claim 8,

wherein the storage element comprises a second transistor and a capacitor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein a first terminal of the first transistor is electrically connected to a second wiring,

wherein a second terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein a first terminal of the second transistor is electrically connected to a third wiring,

wherein a second terminal of the second transistor is electrically connected to the second wiring,

wherein a first electrode of the capacitor is electrically connected to the gate of the second transistor,

wherein a second electrode of the capacitor is electrically connected to a fourth wiring, and

wherein the memory element is configured to output the configuration data through the second wiring.

11. The semiconductor device according to claim 8,

wherein the storage element comprises a second transistor and a third transistor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein a first terminal of the first transistor is electrically connected to a second wiring,

wherein a second terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein a first terminal of the second transistor is electrically connected to a third wiring,

wherein a second terminal of the second transistor is electrically connected to a first terminal of the third transistor,

wherein a second terminal of the third transistor is electrically connected to a fourth wiring,

wherein a gate of the third transistor is electrically connected to a fifth wiring, and

wherein the memory element is configured to output the configuration data through the fourth wiring.

12. The semiconductor device according to claim 8,

wherein the storage element comprises a second transistor and a third transistor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein a first terminal of the first transistor is electrically connected to a second wiring,

wherein a second terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein a first terminal of the second transistor is electrically connected to a third wiring,

wherein a second terminal of the second transistor is electrically connected to a first terminal of the third transistor,

wherein a second terminal of the third transistor is electrically connected to the second wiring,

wherein a gate of the third transistor is electrically connected to a fourth wiring, and

wherein the memory element is configured to output the configuration data through the second wiring.

13. The semiconductor device according to claim 8,

wherein the storage element comprises a capacitor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein a first terminal of the first transistor is electrically connected to a second wiring, and

wherein a second terminal of the first transistor is electrically connected to a first electrode of the capacitor.

14. The semiconductor device according to claim 8,

wherein the selection circuit comprises a first input terminal, a second input terminal, and an output terminal,

wherein the first input terminal is configured to receive a first voltage from an output terminal of the first logic element,

wherein the second input terminal is configured to receive a second voltage,

wherein the selection circuit is configured to output the first voltage to an input terminal of the second logic element while the configuration data is first data, and

wherein the selection circuit is configured to output the second voltage to the input terminal of the second logic element while the configuration data is second data.

15. A semiconductor device comprising:

a logic element; and

a memory element comprising a first storage element and a second storage element,

wherein the memory element is configured to store first configuration data in the first storage element and second configuration data in the second storage element,

wherein the memory element is configured to output one of the first configuration data and the second configuration data,

wherein the logic element is configured to receive the one of the first configuration data and the second configuration data, change a function of the logic element after the logic element receives the first configuration data, and change the function of the logic element after the logic element receives the second configuration data, and

wherein the first storage element comprises a first transistor comprising an oxide semiconductor layer.

16. The semiconductor device according to claim 15,

wherein the first storage element comprises a second transistor and a capacitor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein a first terminal of the first transistor is electrically connected to a second wiring,

wherein a second terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein a first terminal of the second transistor is electrically connected to a third wiring,

wherein a second terminal of the second transistor is electrically connected to a fourth wiring,

wherein a first electrode of the capacitor is electrically connected to the gate of the second transistor,

wherein a second electrode of the capacitor is electrically connected to a fifth wiring, and

wherein the memory element is configured to output the first configuration data through the fourth wiring.

17. The semiconductor device according to claim 15,

wherein the first storage element comprises a second transistor and a capacitor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein a first terminal of the first transistor is electrically connected to a second wiring,

wherein a second terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein a first terminal of the second transistor is electrically connected to a third wiring,

wherein a second terminal of the second transistor is electrically connected to the second wiring,

wherein a first electrode of the capacitor is electrically connected to the gate of the second transistor,

wherein a second electrode of the capacitor is electrically connected to a fourth wiring, and

wherein the memory element is configured to output the first configuration data through the second wiring.

18. The semiconductor device according to claim 15,

wherein the first storage element comprises a second transistor and a third transistor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein a first terminal of the first transistor is electrically connected to a second wiring,

wherein a second terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein a first terminal of the second transistor is electrically connected to a third wiring,

wherein a second terminal of the second transistor is electrically connected to a first terminal of the third transistor,

wherein a second terminal of the third transistor is electrically connected to a fourth wiring,

wherein a gate of the third transistor is electrically connected to a fifth wiring, and

wherein the memory element is configured to output the first configuration data through the fourth wiring.

19. The semiconductor device according to claim 15,

wherein the first storage element comprises a second transistor and a third transistor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein a first terminal of the first transistor is electrically connected to a second wiring,

wherein a second terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein a first terminal of the second transistor is electrically connected to a third wiring,

wherein a second terminal of the second transistor is electrically connected to a first terminal of the third transistor,

wherein a second terminal of the third transistor is electrically connected to the second wiring,

wherein a gate of the third transistor is electrically connected to a fourth wiring, and

wherein the memory element is configured to output the first configuration data through the second wiring.

20. The semiconductor device according to claim 15,

wherein the first storage element comprises a capacitor,

wherein a gate of the first transistor is electrically connected to a first wiring,

wherein a first terminal of the first transistor is electrically connected to a second wiring, and

wherein a second terminal of the first transistor is electrically connected to a first electrode of the capacitor.

21. The semiconductor device according to claim 15,

wherein the logic element comprises a selection circuit,

wherein the selection circuit comprises a first input terminal, a second input terminal, and an output terminal,

wherein the first input terminal is configured to receive a first voltage,

wherein the second input terminal is configured to receive a second voltage,

wherein the selection circuit is configured to output the first voltage after the logic element receives the first configuration data, and

wherein the selection circuit is configured to output the second voltage after the logic element receives the second configuration data.